Fully-Depleted SOI-MOSFET Model for Circuit Simulation and its Application to 1/f Noise Analysis

Abstract

We have developed a fully-depleted SOI-MOSFET model HiSIM-SOI for circuit simulation by solving the potential distribution along all three important SOI-surfaces selfconsistently. Besides comparison to measured I-V data, the model is verified with 1/f noise analysis, sensitive to the carrier concentration and distribution along the channel. The carrier concentration increase, due to confinement of the silicon layer, results in enhanced 1/f noise in comparison with the bulk-MOSFET. Our results show that further reduction of the silicon-layer thickness for achieving higher driving capability will cause unavoidable enhancement of the noise.