For the first time, we demonstrate standard cell gate density of 3650 KGate/mm 2 and SRAM cell of 0.124 μm 2 for 32nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.
We report TaC x /HfSiON gate stack CMOS device with simplified gate 1 st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate
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