A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process

Abstract

For the first time, we demonstrate standard cell gate density of 3650 KGate/mm 2 and SRAM cell of 0.124 μm 2 for 32nm CMOS platform technology. Both advanced single exposure (SE) lithography and gate-first metal gate/high-k (MG/HK) process contribute to reduce total cost per function by 50% from 45nm technology node, which is unattainable by dual exposure (DE) lithography or double patterning (DP) and poly/SiON gate stack.

Effect of Statistical Dopant Fluctuations on Threshold Voltage of Emerging Devices

“…Figure 4 shows an excellent agreement of the mismatch data for SH-MOSFETs with the validation data of identical set of transistor-pairs at the comparable advanced CMOS technology node. Also, the value of the mismatch coefficient, A vt ≅ 1.33 mV × µm for SH-MOSFET baseline technology agrees very well with the reported value of about 1.3 mV × µm for the legacy devices of comparable CMOS technologies [7], [38]. Furthermore, the reported value of A vt for comparable HK/MG SOI-MOSFET technology is in the range of 1.3-1.4 mV × µm [7], [39], [40].…”

“…An exhaustive search on V th mismatch reported a minimum value of A vt ≅ 2.0 mV × µm for silicon dioxide (SiO 2 ) gate dielectric and polysilicon gate MOSFETs of advanced conventional CMOS technology at the nanometer node [7]. Another experimental study demonstrated that the value of V th -mismatch in SiO 2 /polysilicon-gate MOSFETs is reduced by about 35% using HK/MG process [38]. Since HK/MG is assumed for all technologies in this study, then considering a 35% reduction in the reported value of V th -mismatch of SiO 2 /Polysilicon-gate MOSFETs, the value of A vt for the same reported technology [7] with HK/MG process can be shown to be about 1.3 mV × µm.…”

Towards automatic gain control low-power amplifier in 130 nm CMOS technology

“…The current trend of shrinking the minimum channel length of MOS transistors avails a tremendous scale of integration for digital circuits and also a higher operation speed for analog and RF circuits. However, it also introduces numerous drawbacks from the analog design point of view such as the necessity of low value of the power supply voltage, greater fabrication process variations, exponentially rising values of subthreshold leakage current and others [1], [2]. These phenomena negatively affect the dynamic range of processable input signal, noise properties, power supply rejection and other parameters, since the threshold voltage of MOS transistors does not follow the trend of supply voltage downscaling [3].…”

Accurate projection of V<inf>ccmin</inf> by modeling &#x201C;dual slope&#x201D; in FinFET based SRAM, and impact of long term reliability on end of life V<inf>ccmin</inf>

“…Vccmin projection of SRAM array is known to be very difficult especially at high yield target, as the SRAM array yield shows two different slopes ( Fig. 1) with respect to operation Vcc scaling [2] and the mechanism of this behavior is not well understood. As lowering Vcc is important for low power design especially for scaled SRAM bitcell, it's utmost important to understand the dual slope issue in SRAM yield and project Vccmin accurately.…”