65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

Yanagiya, N.; Matsuda, Shôichi; Inaba, S.; Takayanagi, Motowo; Mizushima, Ichiro; Ohuchi, K.; Okano, K.; Takahasi, K.; Morifuji, E.; Kanda, M.; Matsubara, Y.; Habu, M.; Nishigoori, M.; Honda, Kenji; Tsuno, H.; Yasumoto, Koji; Yamamoto, Takeshi; Hiyama, K.; Kokubun, K.; Suzuki, Tsuneo; Yoshikawa, Jun; Sakurai, Takayasu; Ishizuka, T.; Shoda, Y.; Moriuchi, M.; Kishida, M.; Matsumori, Hiroaki; Harakawa, H.; Oyamatsu, H.; Nishida, Naoki; Yamada, Shigeru; Noguchi, T.; Okamoto, H.; Kakumu, M.

doi:10.1109/iedm.2002.1175778

Cited by 19 publications

(7 citation statements)

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“…15a-c, respectively. It is assumed that the process integration of each generation is based on that of Toshiba's CMOS platform; CMOS5 [20], CMOS6 [21], and CMOS7. It is important to note that the thickness of the gate oxide, the silicon, and the buried oxide must be shrunk in order to keep the signal constant as the operation voltage is reduced.…”

Section: Estimation Of the Scalability Of Fbcmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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Section: Estimation Of the Scalability Of Fbcmentioning

confidence: 99%

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Hamamoto

Ohsawa

2009

Solid-State Electronics

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“…(29) along with the short-channel effects, gives excellent match for sub-100 nm devices [86]. Figure 29 compares the I-V characteristics obtained by this method (solid line) with experimental data (dots) obtained from [89] for a channel length L=30 nm, t ox =1 nm, and N A =1.5×10 18 /cm 3 .…”

Section: Surface Potential-based Modelsmentioning

confidence: 66%

“…This has been achieved starting with the relationship for gate voltage given by [91] [86] with experimental data (dots) obtained from [89]. …”

Section: Charge-based Modelsmentioning

confidence: 99%

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Srikantaiah

DasGupta

2012

IETE Tech Rev

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In this paper, the quantum mechanical (QM) effects in bulk MOSFETs and their modeling approaches in the compact modeling framework are reviewed. As the device dimensions are scaled to the sub-100 nm range, QM effects affect the device properties, such as effective oxide thickness, inversion layer charge density and profile, threshold voltage, effective bandgap, gate capacitance, mobility, surface potential, subthreshold characteristics, drain current, and gate leakage current. The classical theory is no longer sufficient for accurate modeling of these device characteristics. In this paper, models which have incorporated QM effects to obtain the device characteristics are discussed and compared. The roles of QM effects in affecting some of the device properties are also presented. KeywordsBulk MOSFETs, Quantum mechanical effect, Review on compact modeling. ( ) , which is used to solve eqn. (1) by numerical methods. Only certain energy levels, denoted by E ij , satisfy the Schrödinger equation and correspond to the energy levels of the sub-bands. Here, i=L for the lower valley and i=H for the higher valley, while j=0, 1, 2, 3…, corresponds the sub-band number. The electron concentration n y IETE TECHNICAL REVIEW | VOL 29 | ISSUE 1 | JAN-FEB 2012 AUTHORS Jayadeva Gowrapura Srikantaiah received the B.E. degree in electronics and communication engineering from NMAM Institute of Technology, Nitte, in 1990, M.Tech degree in digital electronics and advanced communication from the Karnataka Regional Engineering College, Surathkal (Present NITK), in 1995, both were affiliated to Mangalore University, India and Ph.D degree from I.I.T. Madras in 2010. His Ph.D. dissertation was on analytical models incorporating quantum mechanical effects for short n-channel MOSFETS. He joined as a lecturer in NMAM Institute of Technology, Nitte, in 1990 and later as Assistant Professor at JNNCE Shimoga in 1998. He has been a Faculty member in the department of electronics and communication engineering, Nagarjuna College of Engineering and Technology, Bangalore, since September 2010 and is currently a Professor and Head. His research interests are modeling and simulation of bulk and SOI MOSFETs including quantum mechanical effects and low power VLSI design.

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“…DRAM trench capacitor cells have apparent advantages for integration with high-performance microprocessing units (MPUs), static random access memories (SRAMs), and analog devices. 5) To meet the demands of diminishing pattern size of such devices, Si deep-trench etching processes for smaller devices were studied. In the Si trench etching of 190-nmdiameter hole patterns, we have successfully achieved fine profiles without any sidewall erosion; however, sidewall erosions were observed for smaller trenches of 140-nmdiameter holes.…”

mentioning

confidence: 99%

“…The film deposited on the etched Si sidewall inhibits etching reactions on the sidewall and prevents undercut profile formation. [5][6][7][8][9][10] The deposited film is mainly composed of redeposited etch products including F and Br, resulted in SiBrFO composition in the etching processes using HBr=SF 6 =O 2 plasma.…”

mentioning

confidence: 99%

Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF₆/O₂ plasma

Sakai

Yahashi

Shimonishi

et al. 2018

Jpn. J. Appl. Phys.

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A Si deep-trench etching process using HBr/SF6/O2 plasma was studied. It was found that when the hole trench width was decreased from 190 to 140 nm, erosions at the topmost part of the Si hole sidewall were observed at an incidence of 10 ppm, which was checked from top-down views of 928 million hole shapes per wafer. It was confirmed that when the cathode temperature was increased to 140 °C, no Si erosion occurred. It was found that etching at a higher temperature reduced the halogen content in the film deposited on the sidewall, making the film more protective, and suppressed Si erosion.

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65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

Cited by 19 publications

References 0 publications

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF₆/O₂ plasma

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65 nm CMOS technology (CMOS5) with high density embedded memories for broadband microprocessor applications

Cited by 19 publications

References 0 publications

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Overview and future challenges of floating body RAM (FBRAM) technology for 32nm technology node and beyond

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF6/O2 plasma

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Effect of substrate temperature on sidewall erosion in high-aspect-ratio Si hole etching employing HBr/SF₆/O₂ plasma