Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL

Goto, Masakazu; Tatsumura, Kosuke; Kawanaka, S.; Nakajima, K.; Ichihara, Reika; Yoshimizu, Yasuhito; Onoda, H.; Nagatomo, K.; Sasaki, Takahiro; Fukushima, Takashi; Nomachi, Akiko; Inumiya, Seiji; Oguma, H.; Miyashita, K.; Harakawa, H.; Inaba, S.; Ishida, Takeshi; Azuma, A.; Aoyama, T.; Koyama, Masahiro; Eguchi, Kazuhiro; Toyoshima, Y.

doi:10.1109/vlsit.2008.4588591

Cited by 7 publications

(4 citation statements)

References 8 publications

(3 reference statements)

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“…10, a lower PEALD temperature can suppress the side-edge oxidation of a metal gate electrode and a high-k dielectric during PEALD, leading to the improvement in I on -I off characteristics. 26) In order to further improve I on -I off characteristics, the ALD-SiO film deposited at 100 C was used as an OSS film. As the result, the I on of the nMOSFET with the ALD-SiO OSS film deposited at 100 C was 12% higher than that of the nMOSFET with the ALD-SiO OSS film deposited at 200 C. This result indicates that a lower deposition temperature of a SiO OSS film is effective for improving I on -I off characteristics.…”

Section: Resultsmentioning

confidence: 99%

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

Murata

Miyagawa

Nishida

et al. 2010

Jpn. J. Appl. Phys.

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We have investigated the characteristics of silicon oxide films deposited by plasma-enhanced atomic layer deposition (PEALD) and plasma-enhanced chemical vapor deposition (PECVD) as offset spacer films of high-k/metal gate stacks. From the results of bonding structure analysis, the silicon oxide film deposited by PEALD has been found to be composed of a Si–O bond network of the stoichiometric silicon oxide film. On the other hand, the silicon oxide film deposited by PECVD is considered to contain suboxide bond structures. From the results of physical and mechanical evaluations, the silicon oxide film deposited by PEALD exhibits a lower wet etch rate, a higher film density, a lower dielectric constant, a smaller amount of water in the film, and a higher elastic modulus than that deposited by PECVD. PEALD showed excellent thickness controllability. From these results, the silicon oxide film deposited by PEALD has higher quality and is more suitable for use as an offset spacer than that deposited by PECVD. X-ray photoelectron spectroscopy showed that the surface oxidation of a titanium nitride film, which is used as a metal gate electrode, during PEALD can be suppressed by using a lower PEALD temperature. Finally, we have demonstrated that the drain current of a high-k/metal gate transistor with a silicon oxide offset spacer deposited by PEALD is markedly increased, compared with that with a high-temperature-deposited silicon oxide offset spacer.

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Section: Resultsmentioning

confidence: 99%

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

Murata

Miyagawa

Nishida

et al. 2010

Jpn. J. Appl. Phys.

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“…It is reported that the strain effects in short channel devices are enhanced by eliminating fixed charges inside HfSiON [73] , which is also material dependent. And the reliability issue of strained channel device has been investigated.…”

Section: Mobility Enhancement Technologymentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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“…Not only gate leakage current but also mobility has been improved by material selection and interface layer modulation under metal-gate/high-k [1]. However, the last issue still remaining is reliability problems.…”

Section: Introductionmentioning

confidence: 99%

“…High-k gate dielectrics has emerged as replacement for the conventional SiON gate oxides because it can reduce gate leakage significantly but also accelerates scaling-down of the equivalent oxide thickness (EOT) at the same time. Not only gate leakage current but also mobility has been improved by material selection and interface layer modulation under metal-gate/high-k [1]. However, the last issue still remaining is reliability problems.…”

Section: Introductionmentioning

confidence: 99%

(Invited) A Study of Dielectric Breakdown Mechanisms in MG/HK MISFETs: From the Viewpoint of TDDB Statistics

Izumi¹,

Kato²,

Nakasaki³

et al. 2010

ECS Trans.

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The Time Dependent Dielectric Breakdown mechanisms of n/pFETs having high-k gate dielectrics have been studied through the Weibull distribution. From the thickness dependence of Weibull β, it is found that the breakdown in n-FETs and p-FETs is mostly determined by the breakdown of high-k layer and interfacial layer (I.L.), respectively. Furthermore, Weibull β in p-FETs is found to be independent of the injected carrier ratio (J hole /J electron ) while those in n-FETs strongly depend on this ratio. Improvement of Weibull β through the control of the injected carrier ratio together with metal gate application leads to extremely longer lifetime in nFETs. Improvement of average T bd through the control of hydrogen concentration in high-k leads to longer life time also in p-FETs.

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Impact of tantalum composition in TaC/HfSiON gate stack on device performance of aggressively scaled CMOS devices with SMT and strained CESL

Abstract: We report TaC x /HfSiON gate stack CMOS device with simplified gate 1 st process from the viewpoints of fixed charge generation and its impact on the device performance. Moderate

Cited by 7 publications

References 8 publications

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

Low-Temperature Silicon Oxide Offset Spacer Using Plasma-Enhanced Atomic Layer Deposition for High-k/Metal Gate Transistor

Challenges of 22 nm and beyond CMOS technology

(Invited) A Study of Dielectric Breakdown Mechanisms in MG/HK MISFETs: From the Viewpoint of TDDB Statistics

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