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High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

With the goal to render the ReRAM memory integrable with CMOS backend and compatible with current BEOL metal choices (Cu, Ta, Ti, W), we have chosen the well-behaved and well-characterized Cu/TaO x /Pt ReRAM cell as a benchmark device and have replaced the active (Cu) and inert (Pt) electrodes with Ta and Ti electrodes. Five derivative devices were manufactured including: Pt/TaO x /Pt, Cu/TaO x /Ti, Cu/TaO x /Ta, Ta/TaO x /Pt, and Ti/TaO x /Pt. Out of these five devices, only the Ti/TaO x /Pt produced reliable set and reset switching characteristics. Nevertheless, the switching behavior of the other derivative devices provides a great deal of insight into the formation, shape and rupture of conductive filaments in ReRAM devices which would be difficult to gain otherwise from only one type of a device. The present findings are compared with results on the same and similar devices reported elsewhere in the literature.

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