The automotive environment is particularly challenging in terms of requested reliability for electronic components. Flash memories commonly exploited in this framework are subject to this paradigm as well. In semiconductor memories erratic bits are infamously known as a major reliability threat to be handled by repair strategies which spans from static redundancy to dynamic correction codes. Both resources are limited in their amount and correction strength, therefore their usage must be properly tailored. In this work we propose a signature classification methodology for erratic bits that will help the choice of the best repair strategy for each bit, reducing when possible the usage of unnecessary correction resources. This methodology will also turn into a decrease of the chip error probability as demonstrated by an accurate modeling procedure.
The erratic bits (EB) phenomenon in nonvolatile memory devices (NVMs) has been evidenced in several technologies as a main reliability detractor. Usually, this issue is handled by repair strategies, which spans from static redundancy to dynamic correction codes. This evidences a tradeoff in a reliability/ performance domain that is due to the limitation in the repair resources amount and correction strength. In this paper, we expose this tradeoff in different NVM technologies such as embedded NOR Flash and phase-change memory devices through accurate EB testing, signature classification procedure, and chip failure rate estimation.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.