Modeling Erratic Bits Temperature Dependence for Monte Carlo Simulation of Flash Arrays

Zambelli, Cristian; Koebernik, G.; Ullmann, R.; Bauer, Matthias; Tempel, G.; Olivo, P.

doi:10.1109/led.2012.2237541

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…These results are in agreement with the physical background of the erratic bits phenomenon. Large voltage steps induce high electric field variations in the tunnel oxide during soft-programming and higher AHHI currents, therefore the insurgence of multiple SCP ascribed either to progressive positive charge build ups [17] or multiple charge clusters creation in the tunnel oxide [22] becomes more probable. On the contrary, small voltage steps during soft-programming are known to trigger less failures [23] thanks to the electric field variations reduction, and consequently the lowering of AHHI currents that lessens positive charge creation and reduces the slope change events.…”

Section: A the Role Of The Soft-programming Voltage Step Granularitymentioning

confidence: 99%

Characterization of the Over-Erase Algorithm in FN/FN Embedded <sc>nor</sc> Flash Arrays

Zambelli

Olivo

2015

IEEE Trans. Device Mater. Relib.

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The over-erase algorithm is the state of the art procedure exploited in NOR Flash architectures to increase the memory reliability against the over-erase phenomenon mainly caused by either fast or erratic bits. In FN/FN architectures, since the soft-programming operation involved in the algorithm uses the same physical mechanism of the erase operation, its execution potentially triggers additional failures. In this paper, a detailed characterization of the soft-programming failures is provided by categorizing their statistical occurrence in order to capture their relationship with the failures exposed after the execution of the algorithm. A model of the failure rate is then derived to provide a rough guideline for over-erase algorithm optimization in terms of performance and reliability.

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Section: A the Role Of The Soft-programming Voltage Step Granularitymentioning

confidence: 99%

Characterization of the Over-Erase Algorithm in FN/FN Embedded <sc>nor</sc> Flash Arrays

Zambelli

Olivo

2015

IEEE Trans. Device Mater. Relib.

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“…The simulation of erratic behaviors in large Flash arrays has been extensively performed by statistical models mainly relying on Monte Carlo simulation methods [11], [15], [16] that, even if accurate, are not suitable for circuit simulations and fast compact modeling.…”

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confidence: 99%

A Compact Model for Erratic Event Simulation in Flash Memory Arrays

Zambelli

Vincenzi

Olivo

2014

IEEE Trans. Electron Devices

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The simulation of the erratic bits phenomenon in Flash memory arrays for reliability projections has been a matter of study in the last decade from many standpoints. However, the majority of the developed simulation framework lacked both a direct link with the physics underlying the phenomenon and an easy integration with circuit simulators for fast analysis. In this paper, we have developed a compact model for erratic events starting from the PSP-model description of a Flash cell using Verilog-A. The model has been focused on the reproduction of the overerase phenomenon in a 90-nm NOR Flash array. Its accurate and fast simulation capabilities allowed the evaluation of the array reliability against the erratic erase operation

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Temperature-insensitive reading of a flash memory cell

Zhang¹,

Chen²,

Zhu³

et al. 2023

J. Semicond.

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The temperature characteristics of the read current of the NOR embedded flash memory with a 1.5T-per-cell structure are theoretically analyzed and experimentally verified. We verify that for a cell programmed with a “10” state, the read current is either increasing, decreasing, or invariable with the temperature, essentially depending on the reading overdrive voltage of the selected bitcell, or its programming strength. By precisely controlling the programming strength and thus manipulating its temperature coefficient, we propose a new setting method for the reference cells that programs each of reference cells to a charge state with a temperature coefficient closely tracking tail data cells, thereby solving the current coefficient mismatch and improving the read window.

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Modeling Erratic Bits Temperature Dependence for Monte Carlo Simulation of Flash Arrays

Cited by 3 publications

References 8 publications

Characterization of the Over-Erase Algorithm in FN/FN Embedded <sc>nor</sc> Flash Arrays

Characterization of the Over-Erase Algorithm in FN/FN Embedded <sc>nor</sc> Flash Arrays

A Compact Model for Erratic Event Simulation in Flash Memory Arrays

Temperature-insensitive reading of a flash memory cell

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