A Compact Model for Erratic Event Simulation in Flash Memory Arrays

Zambelli, Cristian; Vincenzi, Tommaso; Olivo, P.

doi:10.1109/ted.2014.2356211

Cited by 5 publications

(3 citation statements)

References 26 publications

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“…Among them, the Random Telegraph Noise (RTN) related to filling/empting of tunnel oxide traps affects the V T distributions stability few microseconds after the application of the programming pulse, creating distribution tails below the target verification level [52], [53], [54], [55]. Additionally, positive trapped charge in the tunnel oxide during cycling results in a modified FN tunnel dynamics that may trigger erratic effects [33], [56], [57], [58]. These sporadic mechanisms, that may potentially affect any cell in the array, have a random and transient nature; they can occur during any programming pulse and they may produce threshold shifts larger than expected, with the risk of programming some cells with a threshold voltage larger than the desired one.…”

Section: B Reliability Effectsmentioning

confidence: 99%

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

et al. 2017

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Solid-state drives (SSDs) faced an astonishing development in the last few years, becoming the cornerstone to new paradigms and markets of the information technology, such as cloud computing and big data centers. So far, the SSD design approach has focused on the optimization of the Flash translation layer, the firmware devoted to fulfill the compatibility with traditional hard-disk drives. For hyperscaled SSDs this strategy is no longer valid since their performance and reliability are strictly linked to that of the NAND Flash memories that constitute the storage medium, in particular when the multilevel cell paradigm is considered. For this reason, the design flow must follow a bottom-up approach that, starting from an accurate knowledge of the time and use dependent reliability of the NAND Flash memories, selects the most appropriate error correction strategy to extend the SSD lifetime while reducing its performance degradation. Then, the design flow moves to that of the SSD controller and of the interface toward the host where the application is running. This paper will thoroughly discuss this bottom-up approach, and finally, it will show how it is possible to leverage new approaches, such as the software-defined storage system that, by exploiting a hardware/software codesign of the SSD controller architecture and of the host application, will be able to revolutionize the traditional computer/memory interaction

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Section: B Reliability Effectsmentioning

confidence: 99%

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

et al. 2017

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“…This effect can be represented by a sudden modification of the soft-programming kinetics slope, whose nominal value, in the central region of the kinetics, mainly depends on the OEA step voltage granularity [18]. Such a slope change depends on the positive charge cluster properties present in the tunnel oxide [14], [19], [20], resulting in a temporary increase of the equivalent OEA voltage stepping, thus lowering the algorithm control on the over-erase recovery kinetics.…”

Section: Soft-programming Failures Classificationmentioning

confidence: 99%

Characterization of the Over-Erase Algorithm in FN/FN Embedded <sc>nor</sc> Flash Arrays

Zambelli

Olivo

2015

IEEE Trans. Device Mater. Relib.

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The over-erase algorithm is the state of the art procedure exploited in NOR Flash architectures to increase the memory reliability against the over-erase phenomenon mainly caused by either fast or erratic bits. In FN/FN architectures, since the soft-programming operation involved in the algorithm uses the same physical mechanism of the erase operation, its execution potentially triggers additional failures. In this paper, a detailed characterization of the soft-programming failures is provided by categorizing their statistical occurrence in order to capture their relationship with the failures exposed after the execution of the algorithm. A model of the failure rate is then derived to provide a rough guideline for over-erase algorithm optimization in terms of performance and reliability.

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“…Charge-trap flash (CTF) memories are considered to represent the promising alternative in order for eventually replacing the floating-gate (FG) flash memory technologies in the near future owing to its higher device scalability and are targeted by developments of the most recent three-dimensional (3D) array architectures indeed. [1][2][3][4][5][6][7][8][9] Various device structures and charge trapping layer materials have been adopted for advancing the CTF memories and different physical mechanisms have been closely studied in the respective cell operations. In this work, a highly compact and accurate circuit model of CTF memory cell is proposed, in consideration of the transient behaviors for describing the program operations.…”

Section: Introductionmentioning

confidence: 99%

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

Kim

Lee

Kim³

et al. 2016

Jpn. J. Appl. Phys.

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In this paper, a highly reliable circuit model of gate-all-around (GAA) charge-trap flash (CTF) memory cell is proposed, considering the transient behaviors for describing the program operations with improved accuracy. Although several compact models have been reported in the previous literature, time-dependent behaviors have not been precisely reflected and the failures tend to get worse as the operation time elapses. Furthermore, the developed SPICE models in this work have been verified by the measurement results of the fabricated flash memory cells having silicon–oxide–nitride–oxide–silicon (SONOS). This more realistic model would be beneficial in designing the system architectures and setting up the operation schemes for the leading three-dimensional (3D) stack CTF memory.

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A Compact Model for Erratic Event Simulation in Flash Memory Arrays

Cited by 5 publications

References 26 publications

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

Characterization of the Over-Erase Algorithm in FN/FN Embedded <sc>nor</sc> Flash Arrays

Highly compact and accurate circuit-level macro modeling of gate-all-around charge-trap flash memory

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