Abstract:The automotive environment is particularly challenging in terms of requested reliability for electronic components. Flash memories commonly exploited in this framework are subject to this paradigm as well. In semiconductor memories erratic bits are infamously known as a major reliability threat to be handled by repair strategies which spans from static redundancy to dynamic correction codes. Both resources are limited in their amount and correction strength, therefore their usage must be properly tailored. In … Show more
“…The analysis of the EB for further classification procedures has been performed on different storage-concept test vehicles to prove the general validity of the methodology proposed in [6], where the study was focused on embedded Flash memories belonging to a mature technology node. The first test vehicles population are automotive-quality embedded NOR Flash arrays manufactured with a 90nm process, and integrated on flagship System-On-Chip products.…”
Section: Technologies Under Studymentioning
confidence: 99%
“…A viable solution to discriminate the EB dependently on their signature has been already explained in [6]. That methodology is based on the application of a Markov chain-based EB detection model [17] which can extract, for each EB, two signature parameters identified as: i) the Presence Ratio (P R), that is defined as the ratio of the erratic event occurrences during the test with respect to the total erase cycles number; ii) the Time of Life (T oL), that is defined as the maximum number of consecutive erase cycles displaying an erratic behavior.…”
Section: Signature Classificationmentioning
confidence: 99%
“…4. To discern whether an EB features a proper signature it has been proposed to use an average discrimination criterion (e.g., short T oL means shorter than the average, and low P R means lower than the average) in which the calculation of the expected value for T oL and P R took place on the EB population [6]. This solution holds true if the statistical distributions of the signature parameters display a near zero-skewness.…”
Section: Signature Classificationmentioning
confidence: 99%
“…The seldom burst nature of EB classified with Signature 1 candidates them to be treated only by the ECC; on the contrary EB featuring Signature 2 have a higher occurrence probability with a predictable failing behavior and therefore can be conveniently treated by redundancy. EB featuring signature 3 are the most hazardous due to their unpredictability and can be handled either by redundancy, proving that there is some space left, or only by the ECC dependently on the reliability/performance trade-off requirements [6].…”
Section: Signature Classificationmentioning
confidence: 99%
“…In [6] it has been demonstrated that a classification methodology for the EB, based on the analysis of the features constituting the bit signature, can be exploited to speculate the most efficient repair strategy for each erratic signature class, reducing when possible the redundancy usage.…”
The erratic bits (EB) phenomenon in nonvolatile memory devices (NVMs) has been evidenced in several technologies as a main reliability detractor. Usually, this issue is handled by repair strategies, which spans from static redundancy to dynamic correction codes. This evidences a tradeoff in a reliability/ performance domain that is due to the limitation in the repair resources amount and correction strength. In this paper, we expose this tradeoff in different NVM technologies such as embedded NOR Flash and phase-change memory devices through accurate EB testing, signature classification procedure, and chip failure rate estimation.
“…The analysis of the EB for further classification procedures has been performed on different storage-concept test vehicles to prove the general validity of the methodology proposed in [6], where the study was focused on embedded Flash memories belonging to a mature technology node. The first test vehicles population are automotive-quality embedded NOR Flash arrays manufactured with a 90nm process, and integrated on flagship System-On-Chip products.…”
Section: Technologies Under Studymentioning
confidence: 99%
“…A viable solution to discriminate the EB dependently on their signature has been already explained in [6]. That methodology is based on the application of a Markov chain-based EB detection model [17] which can extract, for each EB, two signature parameters identified as: i) the Presence Ratio (P R), that is defined as the ratio of the erratic event occurrences during the test with respect to the total erase cycles number; ii) the Time of Life (T oL), that is defined as the maximum number of consecutive erase cycles displaying an erratic behavior.…”
Section: Signature Classificationmentioning
confidence: 99%
“…4. To discern whether an EB features a proper signature it has been proposed to use an average discrimination criterion (e.g., short T oL means shorter than the average, and low P R means lower than the average) in which the calculation of the expected value for T oL and P R took place on the EB population [6]. This solution holds true if the statistical distributions of the signature parameters display a near zero-skewness.…”
Section: Signature Classificationmentioning
confidence: 99%
“…The seldom burst nature of EB classified with Signature 1 candidates them to be treated only by the ECC; on the contrary EB featuring Signature 2 have a higher occurrence probability with a predictable failing behavior and therefore can be conveniently treated by redundancy. EB featuring signature 3 are the most hazardous due to their unpredictability and can be handled either by redundancy, proving that there is some space left, or only by the ECC dependently on the reliability/performance trade-off requirements [6].…”
Section: Signature Classificationmentioning
confidence: 99%
“…In [6] it has been demonstrated that a classification methodology for the EB, based on the analysis of the features constituting the bit signature, can be exploited to speculate the most efficient repair strategy for each erratic signature class, reducing when possible the redundancy usage.…”
The erratic bits (EB) phenomenon in nonvolatile memory devices (NVMs) has been evidenced in several technologies as a main reliability detractor. Usually, this issue is handled by repair strategies, which spans from static redundancy to dynamic correction codes. This evidences a tradeoff in a reliability/ performance domain that is due to the limitation in the repair resources amount and correction strength. In this paper, we expose this tradeoff in different NVM technologies such as embedded NOR Flash and phase-change memory devices through accurate EB testing, signature classification procedure, and chip failure rate estimation.
Due to the rapid development of hand-held electronic devices, the need for high density, low power, high performance SoCs has pushed the well-established embedded memory technologies to their limits. To overcome the existing memory issues, emerging memory technologies are being developed and implemented. The focus is placed on non-volatile technologies, which should meet the high demands of tomorrow applications. The nonvolatile memory technologies being intensively researched today are the Flash memories and the emerging resistive and magnetic type random access memories. This paper presents an overview of device level operation of these nonvolatile memories, with special emphasis on the fabrication-and aging-induced reliability issues
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