Exposing Reliability/Performance Tradeoff in Non-Volatile Memories Through Erratic Bits Signature Classification

Abstract

The erratic bits (EB) phenomenon in nonvolatile memory devices (NVMs) has been evidenced in several technologies as a main reliability detractor. Usually, this issue is handled by repair strategies, which spans from static redundancy to dynamic correction codes. This evidences a tradeoff in a reliability/ performance domain that is due to the limitation in the repair resources amount and correction strength. In this paper, we expose this tradeoff in different NVM technologies such as embedded NOR Flash and phase-change memory devices through accurate EB testing, signature classification procedure, and chip failure rate estimation.

Is Consumer Electronics Redesigning Our Cars?: Challenges of Integrated Technologies for Sensing, Computing, and Storage

“…However, from the pure reliability viewpoint, the erase operation has always been an issue for every NOR Flash technology so far [37]. In the last decades, special emphasis has been put on the reduction of the standard erase failure mechanisms by implementing either proper correction algorithms or failure screening techniques aiming at a memory fail rate reduction below 1 ppm [38]. Such activity involves: complex time-consuming recovery algorithms that burden on the erase latency, Error Correction Codes (ECC) design for fast error detection and correction to limit the impact on the read latency, and redundancy-based solutions that increase the costs of the final product where the NVM is embedded.…”

Solid-State Drives: Memory Driven Design Methodologies for Optimal Performance

“…Among them, the Random Telegraph Noise (RTN) related to filling/empting of tunnel oxide traps affects the V T distributions stability few microseconds after the application of the programming pulse, creating distribution tails below the target verification level [52], [53], [54], [55]. Additionally, positive trapped charge in the tunnel oxide during cycling results in a modified FN tunnel dynamics that may trigger erratic effects [33], [56], [57], [58]. These sporadic mechanisms, that may potentially affect any cell in the array, have a random and transient nature; they can occur during any programming pulse and they may produce threshold shifts larger than expected, with the risk of programming some cells with a threshold voltage larger than the desired one.…”

A Compact Model for Erratic Event Simulation in Flash Memory Arrays

“…An application of the proposed compact model turns particularly useful in the evaluation of the erase operation reliability, therefore allowing extended considerations on the best approaches to follow (i.e., soft-programming algorithms or error correction codes [4]) to increase this metric. The case study concerns the evaluation of the bitline current I read when overerased cells share the same bitline of a programmed cell to be read, as shown in Fig.…”