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The impacts of intrinsic threshold voltage (V th) fluctuations in metal oxide semiconductor field effect transistors (MOSFETs) on the static random access memory (SRAM) static noise margin (SNM) are re-examined in the 90 nm to 45 nm technology generations on the basis of the 2003 International Technology Roadmap for Semiconductors (ITRS). The V th fluctuations due to random dopant fluctuations are calculated using the cube model and the deviations in SNM are derived using two-dimensional device simulations and SPICE simulations. It is found that five sigma of SNM deviations is ensured at gate length L g=53 nm in the 90 nm node at β=1.5. It is also demonstrated that, although four sigma of SNM deviations exceeds the average SNM in the 65 nm (L g=32 nm) and 45 nm (L g=22 nm) nodes, four sigma of SNM deviations is ensured by adjusting L g, the power supply voltage (V dd), V th and the drain-induced barrier lowering (DIBL) without using improved MOSFET structures.

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