Re-Examination of Impact of Intrinsic Dopant Fluctuations on Static RAM (SRAM) Static Noise Margin

Abstract

The impacts of intrinsic threshold voltage (V th) fluctuations in metal oxide semiconductor field effect transistors (MOSFETs) on the static random access memory (SRAM) static noise margin (SNM) are re-examined in the 90 nm to 45 nm technology generations on the basis of the 2003 International Technology Roadmap for Semiconductors (ITRS). The V th fluctuations due to random dopant fluctuations are calculated using the cube model and the deviations in SNM are derived using two-dimensional device simulations and SPICE simulations. It is found that five sigma of SNM deviations is ensured at gate length L g=53 nm in the 90 nm node at β=1.5. It is also demonstrated that, although four sigma of SNM deviations exceeds the average SNM in the 65 nm (L g=32 nm) and 45 nm (L g=22 nm) nodes, four sigma of SNM deviations is ensured by adjusting L g, the power supply voltage (V dd), V th and the drain-induced barrier lowering (DIBL) without using improved MOSFET structures.

Recovery and parmanent components of &#x007C;V<inf>th</inf>&#x007C; shifts in pFETs by high-voltage on-state stress

“…In particular, the stability of SRAM cells is largely affected by random V th variability of cell transistors [2][3][4]. Recently, a new concept of a post-fabrication selfimprovement technique of SRAM cell stability by simply applying high voltage to V DD terminal has been proposed and demonstrated [5][6][7][8].…”

Comparison of Minimum Operation Voltage (Vmin) in Fully Depleted Silicon-on-Thin-BOX (SOTB) and Bulk SRAM Cells

“…One of the most significant barriers for further supply voltage (V DD ) scaling in SRAM is the random variability of transistors [1][2][3][4][5][6]. The minimum operation voltage (Vmin) in large scale SRAM cell array is much higher than that in logic circuits [7], which obstructs low voltage operation of SRAM and forces very complicated circuit design.…”

“…The stability of SRAM cells is usually characterized by static noise margin (SNM) [1][2][3][4][5][6]. However, since the stability of SRAM array is determined by the worst cell in the cell array, it is hard to quantitatively compare the cell stability by merely SNM in different technologies.…”

Gate Length and Gate Width Dependence of Drain Induced Barrier Lowering and Current-Onset Voltage Variability in Bulk and Fully Depleted Silicon-on-Insulator Metal Oxide Semiconductor Field Effect Transistors

“…DIBL variability has a great impact on the circuit performance and static random-access memory (SRAM) stability. 19,20) It has been already reported that DIBL is mainly decided by channel potential profile along the gate length due to RDF. 21) In order to design reliable logic circuits and SRAM, the precise statistical modeling of COV and DIBL variability is essential.…”