A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

“…However, the timing of SAE is sensitive to the process, voltage and temperature (PVT) variations [1,2,3,4,5]. Thus, the optimum SAE timing must be determined according to the PVT variations.…”

“…The V th variation cannot be tracked tightly by the conventional RBL technique [1], which leads to the SRAM access time deterioration and read failure may result, particularly at low supply voltage. In order to reduce timing variation, more designs are proposed, such as a multi-stage replica bitline (MRB) technique in [2] and a digitized replica bitline delay (Digitized-RBD) technique in [3,4]. If the RBL is divided into K stages or the RCs are multiplied by K times according to the MRB and Digitized-RBD technique respectively, the standard deviation (σ) of the SAE timing will be divided by ffiffiffiffi K p compared with that in conventional RBL technique.…”

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing

“…However, this strategy in low voltage operation faced with some new challenges. Firstly, as mentioned in [5], there are some limits on replica cell count due to the lower supply voltage. Secondly, although some timing matching schemes by adding logic gate delay could indeed increase the replica cell count and reduce the variation significantly, they also bring additional area cost.…”

“…Secondly, although some timing matching schemes by adding logic gate delay could indeed increase the replica cell count and reduce the variation significantly, they also bring additional area cost. For example, the stat-of-the-art design of a digitized bit-line delay replica technique in [5] is proposed for suppressing the SAE timing variation. This technique introduces logic gate delay circuits called Timing Multiplier Circuit (TMC) for postponing the SA-enable signal.…”

“…The technique of suppressing the SA timing in previous work [3,4] is not considered to be suitable for the low voltage operation because of the impractical test cost and timing mismatch between the replica bitline and normal one. The state-of-the-art digitized bitline delay replica technique is proposed in [5] for solving the SAE timing problem. Unfortunately, the logic delay of the timing multiplier circuit not only introduces large area overhead, but also brings significant timing variation due to the quantization error and the process variation of logic units.…”