A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

Abstract

A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process-variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process-variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800 mV in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.

Variation-resilient pipelined timing tracking circuit for SRAM sense amplifier

“…As can be seen, the standard deviation of SAE timing generated by pipelined circuit obtains 69.45% improvement compared with that generated by conventional circuit, owing to 235.89 ps reduction. Generally, the delay time of the SAE timing occupies about half of the cycle time [5,6,7,9,10]; hence, the conventional cycle time is 10.52 ns (ð6:26 À 1Þ ns  2). According to [5,6,7,9,10], three-sigma (3) variation existing is assumed for the SAE timing margin; thus, the SAE timing margin is reduced from 2.038 ns (3  2) to 0.623 ns by applying the proposed circuit.…”

“…According [7,8], the mean value and the standard deviation of the conventional SAE timing delay are described as Conv and Conv , respectively.…”

“…However, with the variations of process, voltage and temperature (PVT) existing, the accurate SAE timing is necessary for reliable operation [1,2,3,4,5,6,7,8,9,10]. In order to obtain the optimum timing for SAE, based on the replica bitline (RBL) technique [3], some timing generation circuits [4,5,6,7,8,9,10] were proposed. Reference [5] gives the analyzation of the existing techniques, and proposes an efficient RBL technique without area-overhead.…”

“…As shown, with N-stage pipeline and K times replica cells (RCs) used in each operation, the number of the dummy cell (DC) in proposed circuit, X, is equal to R=M À N Á ðK Á PÞ. What the M means is that the capacitance of left RBL (LRBL) or right RBL (RRBL) [5,6,7] is equal to C RBL =M. R and P are the number of the total rows and the RCs used, respectively, in conventional RBL.…”