MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing

Zhou, Yongliang; Cai, Hao; Liu, Bo; Zhao, Weisheng; Yang, Jun

doi:10.1109/tcsii.2020.2980331

Cited by 6 publications

(3 citation statements)

References 20 publications

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“…where E is the energy barrier, α is the magnetic damping constant, γ is the gyromagnetic ratio, e is the elementary charge, µ B is the Bohr magneton, µ 0 is the permeability of free space, M s is the saturation magnetization, H K is the effective anisotropy field, V is the volume of the free layer, and g = TMR(TMR + 2)/2(TMR + 1) is the spin polarization efficiency factor. Generally, the read operation differentiates the MTJ resistances by converting the resistance states into voltage differences using voltage sensing schemes [66,67]. As presented in Figure 3(b), the bit-cell is read by enabling the word line (WL) and setting the source line (SL) to ground and bit line (BL) to V READ .…”

Section: Implementation Of Mram Hierarchy: An Stt-mram Examplementioning

confidence: 99%

“…Additionally, the performance is highly sensitive to the CMOS-MTJ device variations; e.g., the limited TMR of MTJ leads to a small sensing margin and low V BL swing, which deteriorates the computational accuracy and limits IMC stability. Recently, considerable research has been conducted on MRAM-sensing margin enhancement techniques [66,67,77] to benefit the performance optimization of sensing-based schemes.…”

Section: Sensing-based Schemementioning

confidence: 99%

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A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

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In traditional von Neumann computing architectures, the essential transfer of data between the processor and memory hierarchies limits the computational efficiency of next-generation system-on-a-chip. The emerging in-memory computing (IMC) approach addresses this issue and facilitates the movement of significant data and rapid computations. Among the different memory types, intrinsic energy efficiency is demonstrated by in-magnetic random access memory (MRAM) computing with a low-power spintronic magnetic tunnel junction device and hybrid integration at an advanced complementary metal-oxide semiconductor node. This study reviews state-of-the-art techniques for managing IMC with an emphasis on spin-transfer torque-MRAM computing via design schemes at the bit-cell, circuit, and system levels. In addition, this study presents effective design techniques and potential challenges and demonstrates the existing limitations of in-MRAM computing and potential methods for overcoming these issues. This study also considers the design technology co-optimization from the IMC perspective.

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Section: Implementation Of Mram Hierarchy: An Stt-mram Examplementioning

confidence: 99%

Section: Sensing-based Schemementioning

confidence: 99%

A survey of in-spin transfer torque MRAM computing

Cai

Liu

Chen

et al. 2021

Sci. China Inf. Sci.

Self Cite

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show abstract

“…2(b) and 2(c). Replica bit-line technique is a proper timing scheme for suppressing timing variation and tracking MRAM process fluctuations [29]. Additionally, VBL and VBLB drop to a low level at sensing time, which produces a weak driving ability for NMOS sampling transistors.…”

Section: Conventional Vsamentioning

confidence: 99%