A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers

Niki, Yusuke; Kawasumi, A.; Suzuki, Ai; Takeyama, Y.; Hirabayashi, O.; Kushida, K.; Tachibana, Fumihiko; Fujimura, Y.; Yabe, T.

doi:10.1109/asscc.2010.5716633

Cited by 5 publications

(19 citation statements)

References 12 publications

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“…However, with the value of M increasing, the delay between RBL and normal bitline becomes larger owing to the gate delay of the inverters inserted in every two stages. For this reason, a Digitized-RBD technique is proposed in [3,4]. It utilizes K times RCs in RBL column compared with that in conventional RBL.…”

Section: Conventional Design and Related Rbl Techniquementioning

confidence: 99%

“…On the contrary, more extra access time and energy consumption will be introduced. Unfortunately, assuming that the logical threshold voltage of the inverter is half of supply voltage, the conventional SAE timing variation is difficult to be reduced owing to the upper limit of the RCs count when supply voltage is lowered [4].…”

Section: Conventional Design and Related Rbl Techniquementioning

confidence: 99%

“…The standard deviation of SAE timing of this work is 616.6 ps, which is 41.83% and 17.64% smaller than that in conventional and Dual-RBD technique, respectively. Generally, the SAE timing used is about half of the cycle time [3,4], thus, the cycle time of conventional RBL is 28 ns (14 ns Â 2). In this case, we assume 3 times the standard deviation (σ) for SAE timing margin.…”

Section: Which Is the Same As That In Conventionalmentioning

confidence: 99%

“…However, the timing of SAE is sensitive to the process, voltage and temperature (PVT) variations [1,2,3,4,5]. Thus, the optimum SAE timing must be determined according to the PVT variations.…”

Section: Introductionmentioning

confidence: 99%

“…The V th variation cannot be tracked tightly by the conventional RBL technique [1], which leads to the SRAM access time deterioration and read failure may result, particularly at low supply voltage. In order to reduce timing variation, more designs are proposed, such as a multi-stage replica bitline (MRB) technique in [2] and a digitized replica bitline delay (Digitized-RBD) technique in [3,4]. If the RBL is divided into K stages or the RCs are multiplied by K times according to the MRB and Digitized-RBD technique respectively, the standard deviation (σ) of the SAE timing will be divided by ffiffiffiffi K p compared with that in conventional RBL technique.…”

Section: Introductionmentioning

confidence: 99%

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A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

Peng

Tao

et al. 2015

IEICE Electron. Express

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A novel cascade control replica bitline delay (CCRBD) technique has been proposed to reduce timing process-variation of SRAM sense amplifier in this brief. The main idea of this technique is that both replica bitlines (RBLs) are utilized, and one is cascade controlled by the other. Simulation results show that the timing process-variation of this technique decreases by 41.83% compared with conventional strategy. Simultaneously, the cycle time is also reduced by 19% at the supply voltage of 800 mV in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that with conventional replica bitline technique.

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Section: Conventional Design and Related Rbl Techniquementioning

confidence: 99%

Section: Conventional Design and Related Rbl Techniquementioning

confidence: 99%

Section: Which Is the Same As That In Conventionalmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

Peng

Tao

et al. 2015

IEICE Electron. Express

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Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers

Peng

Tao

et al. 2015

Electron. lett.

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An efficient replica bitline (RBL) technique for reducing the variation of sense amplifier enable (SAE) timing is proposed. Both RBLs and four-fold replica cells compared with the conventional RBL technique are utilised to favour the desired operations. Simulation results show that the standard deviation of SAE can be suppressed by 44.25% and the cycle time is also reduced by ∼30% at a 0.8 V supply voltage in TSMC 65 nm technology. Additionally, the area of the proposed scheme is nearly the same as that of the conventional RBL scheme.Introduction: At present, to achieve fast and low-power read operation, small-swing bitlines and clocked sense amplifiers (SAs) are utilised in SRAM designs. For reliable operation at high speed, the sense amplifier enable (SAE) signal must track the small-swing bitline delay across global and local process, voltage and temperature (PVT) variations [1]. If the SAE arrives early before the bitline voltage difference reaches the SA offset, a read failure may happen. By contrast, unnecessary access time and power consumption will be increased [2][3][4][5]. Generally, the SAE signal is self-timed using the replica bitline (RBL) technique, since it tracks bitline delay better than simple inverter chains [2]. To suppress the timing variation of SAE, a configurable RBL technique by selecting low-variation replica cells (RCs) to drive the RBL is proposed in [1]. Unfortunately, it costs many additional postsilicon tests. A multi-stage RBL technique, with an inverter inserted in each of the two stages, is proposed in [3]. However, it is considered to be unsuitable for low-voltage operations [4]. In [4], with the usage of K times RCs in a replica column and timing multiplier circuit (TMC), a digitised RBL delay (digitised-RBD) technique has been developed. The disadvantage of this scheme is that the quantisation noise as well as the area of the TMC becomes larger as the count of RCs increases [5]. With the RBL segmented into M stages and K times RCs used in each stage, another technique called multiple-stage parallel RBL delay addition is proposed in [5]. The target SAE timing is generated by the timing addition circuit (TAC) constituted of an M × K stages digital delay circuit. Also, the quantisation noise as well as the area of the TAC becomes larger as M and K increase. Considering area efficiency, a novel dual RBL delay (dual-RBD) technique is proposed in [6], which makes the best use of the non-discharged bitline in the conventional RBL technique to reduce the standard deviation of the SAE timing to the conventional RBL's 1/ 2 √ . Nevertheless, because of the doubled capacitance of the RBL, extra access time will be incurred during the pre-charging stage.In this Letter, an efficient RBL technique is presented, which simultaneously utilises four times RCs and the non-discharged bitline of the conventional RBL scheme. Theoretically, the standard deviation of SAE timing can be reduced by 50% compared with that in conventional RBL. In this case, compared with the conventional RBL and dual-RBD ...

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Current mirror‐based compensation circuit for multi‐row read in‐memory computing

et al. 2019

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Multi‐row read plays an important role in in‐memory computing and its precision affects the accuracy of the calculation. In this brief Letter, a discharge compensation method is proposed for the linearisation of multi‐row read operations in static RAM. Current mirrors are added to bitlines to compensate for the discharge voltage. With compensation, the integral non‐linearity decreases by 72% compared with the situation without compensation. In addition, a wordline signal generation circuit based on replica bitline is proposed to reduce area cost.

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A digitized replica bitline delay technique for random-variation-tolerant timing generation of SRAM sense amplifiers

Cited by 5 publications

References 12 publications

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier

Efficient replica bitline technique for variation‐tolerant timing generation scheme of SRAM sense amplifiers

Current mirror‐based compensation circuit for multi‐row read in‐memory computing

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