Current mirror‐based compensation circuit for multi‐row read in‐memory computing

Lin, Zhiting; Fang, Yaqi; Peng, Chunyu; Lu, Wenjuan; Li, Xuan; Wu, Xiulong; Chen, Junning

doi:10.1049/el.2019.2415

Cited by 6 publications

(4 citation statements)

References 15 publications

(13 reference statements)

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“…where LSB is the least significant bit-the ideal unit of change between two adjacent results. We tally the INL of our results and the results of [12,13] in Figure 5, which are all under tt corner conditions and 25 • C The INL of our results was calculated using the data for the calculated ideal line as the Ideal Value and the average result voltage of all possible calculation combinations as the Tested Value. The INL from [13] are under the conditions of VDD = 0.8 V and Last Column in their article, respectively.…”

Section: Resultsmentioning

confidence: 99%

“…Furthermore, they increase the amount of data transferred on-and off-chip, which contrasts with the fundamental targets of CIM, so on-chip solutions are fairly proposed. Related works that have used on-chip circuit methods are as follows: Z. Lin in [12] proposed a current-mirrorbased compensation circuit which provided an extra charge current for the bitline when the voltage is low. In [13], they improved their design by separating the capacitance and the bitline with a cascade current mirror.…”

Section: Recent Techniquesmentioning

confidence: 99%

See 1 more Smart Citation

Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

Zhao

Wang

et al. 2022

Electronics

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To increase the throughput of computing-in-memory (CIM) designs, multi-row read methods have been adopted to increase computation in the analog region. However, the nonlinearity created by doing so degrades the precision of the results obtained. The results of CIM computation need to be precise in order for CIM designs to be used in machine learning circumstances involving complex algorithms and big data sets. In this study, a low computing leakage, wide-swing output compensation circuit is proposed for linearity improvement in such circumstances. The proposed compensation circuit is composed of a current competition circuit (as dynamic feedback of the bitline discharge current), a current mirror (to separate the result capacitor and provide charge current), and an additional pull-down circuit (for better precision in high voltage results). Measurements show that by applying our method, an almost full-swing output with 51.2% nonlinearity decrement compared with no compensation can be achieved. Power consumption is reduced by 36% per round on average and the computing leakage current, after wordlines are deactivated for 1 ns, is reduced to 55% of that when using conventional methods. A figure of merit (FOM) is proposed for analog computing module evaluation, presenting a comprehensive indicator for the computation precision of such designs.

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Section: Resultsmentioning

confidence: 99%

Section: Recent Techniquesmentioning

confidence: 99%

Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

Zhao

Wang

et al. 2022

Electronics

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show abstract

“…However, when the signal margin is less than the input offset of the analog readout circuit, the sensing amplifier (SA) or the ADC, the accuracy of the analog readout operation, decreases, resulting in reduced system-level calculation accuracy. Recently, several studies [4][5][6] identified this problem in the SRAM design and, therefore, designed multiple methods to alleviate non-linear current accumulation. For example, in [5], a current mirror is added to improve the linearity by accelerating the BL discharge in the triode region.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, several studies [4][5][6] identified this problem in the SRAM design and, therefore, designed multiple methods to alleviate non-linear current accumulation. For example, in [5], a current mirror is added to improve the linearity by accelerating the BL discharge in the triode region. However, excessive discharge operations may occur with overcompensation or read breaking.…”

Section: Introductionmentioning

confidence: 99%

A High-Precision Voltage-Quantization-Based Current-Mode Computing-in-Memory SRAM

Zhao,

Gong,

Liu

et al. 2023

Micromachines

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Non-linear distortion of signals is a serious problem in computing-in-memory SRAM (CIM-SRAM) circuits in current mode. This problem greatly limits the performance of calculations and directly affects the computing power of the CIM-SRAM. In this study, the causes of non-linearity and inconsistency were investigated. Based on detailed analyses, we proposed a high-precision, fully dynamic range IV (HFIV) conversion circuit. The HFIV circuit was added to each bit line (BL) for voltage clamping and proportionally mirroring the read current. We applied the structure to numerous prior studies and evaluated them using the 55 nm complementary metal-oxide semiconductor process. The results showed the proposed HFIV circuit could increase the CIM-SRAM’s calculation linearity to 99.92% (8~32 SRAM bit-cells) and 99.8% (32~64 SRAM bit-cells) with a 1.2 V supply.

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A review on SRAM-based computing in-memory: Circuits, functions, and applications

Lin¹,

Tong²,

Zhang³

et al. 2022

J. Semicond.

Self Cite

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Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

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Current mirror‐based compensation circuit for multi‐row read in‐memory computing

Cited by 6 publications

References 15 publications

Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

A High-Precision Voltage-Quantization-Based Current-Mode Computing-in-Memory SRAM

A review on SRAM-based computing in-memory: Circuits, functions, and applications

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