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This paper presents a configurable SRAM for low-voltage operation with constant-negative-level write buffer (CNL-WB) and level programmable wordline driver for single supply (LPWD-SS) operation. CNL-WB is suitable for compilable SRAMs and it improves write margin by featuring an automatic BL-level adjustment for configuration range of four to 512 cells/BL using a replica-BL technique. LPWD-SS optimizes the tradeoff between disturb and write margin of a memory cell, allowing a 60% shorter WL rise time than that of the conventional design [1] at 0.7V. A test-chip is fabricated in a 32nm high-κ metal-gate CMOS technology with a 0.149µm 2 6T-SRAM cell. Measurement results demonstrate a cell-failure rate improvement of two orders of magnitude for an array-configuration range of 64 to 256 rows by 64 to 256 columns.For a low power SoC, a configurable SRAM operating at low voltage is a key component. The characteristic variation of a scaled device has been increasing, thus compromising the low-voltage functionality of high-density SRAMs [2,3]. Functionality and high yield at low supply voltages such as 0.7V has become more difficult to achieve with the degradation of write margin and the optimization between read disturb and write margin. Among recently reported techniques, the scheme that implements BL negative biasing and WL level control [4] is an effective approach [1]. However, the conventional schemes are not suitable for configurable SRAM for two reasons. First, the circuit must be optimized for each different array configuration to create a suitable BL level. Second, the conventional scheme of WL-level control causes rise-time degradation of the WL at low voltage. This paper describes two circuit techniques for coping with the problems, CNL-WB to automatically adjust the BL bias to a suitable level in a wide range of array configurations and LPWD-SS for fast WL activation at low voltage. Figure 19.4.1 shows the circuit schematic of the configurable SRAM. Each I/O block has the BL negative bootstrap circuit named CNL-WB. The BL capacitance monitor working as a replica of a BL generates a signal activating the bootstrap (boost_en). Every WL driver has a pull-down unit (PDU) to lower the WL voltage for optimizing the tradeoff between disturb and write margin. Figure 19.4.2 shows the circuit schematic and simulated waveforms of CNL-WB. One issue of the conventional technique [1] is as follows: when using a negative-bootstrap circuit in a configurable SRAM, the bootstrap capacitance and the timing of activating the signal boost_en must be optimized depending on the memory cell count on a BL. The custom optimization makes this technique unsuitable for compilable SRAMs. Without such optimization, the negative BL level can become too high and results in insufficient write margin. On the other hand, if the level is too low it causes a reliability problem through data corruption on memory cells with unselected WLs on the accessed column. CNL-WB solves this problem with a bootstrap circuit by automatically adjusting the BL ...

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Molecular dynamics simulations using improved Tersoff–Brenner potential parameters were performed to investigate Cl+ etching of a {2×1} reconstructed Si(100) surface. Steady-state Si etching accompanying the Cl coverage of the surface is observed. Furthermore, a steady-state chlorinated reaction layer is formed. The thickness of this reaction layer is found to increase with increasing energy. The stoichiometry of SiClx species in the reaction layer is found to be SiCl:SiCl2:SiCl3=1.0:0.14:0.008 at 50 eV. These results are in excellent agreement with available experimental data. While elemental Si products are created by physical sputtering, most SiClx (0<x<4) etch products are produced by chemical-enhanced physical sputtering.

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