A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

Kawasumi, A.; Yabe, T.; Takeyama, Y.; Hirabayashi, O.; Kushida, K.; Tohata, A.; Sasaki, Takahiro; Katayama, A.; Gou, Fujun; Fujimura, Y.; Otsuka, N.

doi:10.1109/isscc.2008.4523217

Cited by 23 publications

(9 citation statements)

References 7 publications

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“…The derivations suggest that reasonably symmetric sized cells fail to provide sufficient yield at subthreshold supply levels. In order to break the deadlock between the cell size and yield, asymmetric cells are reported in [18], [19] without any analytical proof or design guidelines. An asymmetric 6 T cell with single ended read operation is shown in Fig.…”

Section: E Dependency On Sizingmentioning

confidence: 99%

“…Since the asymmetric 6 T cell uses different access transistors for Read and Write operations, upsizing the Write access transistors (M6) improves the Write SNM without threatening the Read stability. According to (18), making Left inverter (M1, M3) n-strong and Right inverter (M2, M4) p-strong increases the Read SNM. It is worthy to note that the single ended read operation requires an improved sense amplifier.…”

Section: E Dependency On Sizingmentioning

confidence: 99%

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Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Saeidi

Sharifkhani

Hajsadeghi

2014

IEEE Trans. Circuits Syst. I

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A fast statistical method for the analysis of the Read SNM of a 6 T SRAM cell in near/subthreshold region is proposed. The method is based on the nonlinear behavior of the cell. DIBL and body effects are thoroughly considered in the derivation of an accurate closed form solution for the Read Static Noise Margin (SNM) of the near/subthreshold SRAM cell. This method uses the state space equation to derive the Read SNM of the cell as a function of threshold voltage of cell transistors. This function shows the dependency of the Read SNM on sizing, , temperature, and threshold voltage variations. It provides a fast reliability analysis for a cell array of a given size and a supply voltage. It also calculates the accurate value of failure probability of the cell. The analytical results are verified using Monte-Carlo simulations in 45 nm Predictive Technology Models. Index Terms-Analytical modeling, data stability in SRAM, failure probability, random dopant fluctuation (RDF), subthreshold.

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Section: E Dependency On Sizingmentioning

confidence: 99%

Section: E Dependency On Sizingmentioning

confidence: 99%

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Saeidi

Sharifkhani

Hajsadeghi

2014

IEEE Trans. Circuits Syst. I

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“…4.3.1 Fine Grained Bit-Line Architecture Kawasumi et al (2008) utilizes hierarchical bit-lines with an asymmetrical SRAM 6T cell to achieve high speed, low voltage operation. It uses asymmetrical SRAM cell with unit beta ratio with hierarchical divided bit-lines.…”

Section: Hierarchical Divided Bit-lines With Local Assist Circuitrymentioning

confidence: 99%

“…Hierarchical divided bit-lines with local assist circuitry (Kawasumi et al 2008;Ishikura et al 2008;Chang et al 2008 andCosemans et al 2007): addition of an upsized low Vt read buffer as a local assist circuit accelerates the bit-line discharge rate and achieves high performance. The low swing pre-charged global bit-lines as proposed by Cosemans et al (2007) further increases the variability resilience.…”

Section: Introductionmentioning

confidence: 99%

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

Sharma

Catthoor²,

Dehaene

2012

SRAM Design for Wireless Sensor Networks

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“…The cell has two word-lines and is accessed by a two-phase single-ended write and a single-ended read operation. The cell in Figure 1 is one specific implementation An asymmetric 6T with a single word-line (WL) was proposed in [5] that improves both RSNM and WNM at the cost of area. This cell is highly susceptible to half-select related failures (e.g.…”

Section: Introductionmentioning

confidence: 99%

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation

Nalam

Chandra

Pietrzyk

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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of a 6T bitcell that combines asymmetric sizing, two-phased write and single-ended operation. We describe these ideas in the next section before presenting the specific example of our bitcell. AbstractThis paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (VMIN) . Single-ended write is accomplished in two phases using dual word-lines. Finally , we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing , for the same bitcell area.

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A Single-Power-Supply 0.7V 1GHz 45nm SRAM with An Asymmetrical Unit-ß-ratio Memory Cell

Cited by 23 publications

References 7 publications

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Statistical Analysis of Read Static Noise Margin for Near/Sub-Threshold SRAM Cell

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

Asymmetric 6T SRAM with two-phase write and split bitline differential sensing for low voltage operation

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