of a 6T bitcell that combines asymmetric sizing, two-phased write and single-ended operation. We describe these ideas in the next section before presenting the specific example of our bitcell.
AbstractThis paper describes an asymmetric single-ended 6T SRAM bitcell that improves both Read Static Noise Margin (RSNM) and Write Noise Margin (WNM) for the same bitcell area as a conventional symmetric 6T. This improvement is achieved using a single VDD, without employing assist techniques that require multiple voltages. The improvement in noise margins significantly improves the low-voltage robustness and consequently the minimum operating voltage of the SRAM (VMIN) . Single-ended write is accomplished in two phases using dual word-lines. Finally , we propose a differential sensing scheme using a weak reference cell to read the single-ended 6T. A combination of reduced bitline capacitance and increased drive current ensure read delay comparable to conventional differential sensing , for the same bitcell area.
Nonvolatile repair caches require less area than traditional row, column, or block redundancy schemes, to repair random defective memory cells in deep submicron embedded SRAMs and new nonvolatile memories such as FeRAM, MRAM, and OUM. Small memories with few defects can be repaired efficiently in real time by the direct mapped nonvolatile repair cache whereas large memories with many defects can be repaired more effectively and in real time by the N way set associative repair cache. An 8 way set associative repair cache was implemented in the Texas Instruments-Agilent Technologies 64Mbit FeRAM chip.
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