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We report on atomic layer deposited Hf0.5Zr0.5O2 (HZO)-based capacitors which exhibit excellent ferroelectric (FE) characteristics featuring a large switching polarization (45 μC/cm2) and a low FE saturation voltage (∼1.5 V) as extracted from pulse write/read measurements. The large FE polarization in HZO is achieved by the formation of a non-centrosymmetric orthorhombic phase, which is enabled by the TiN top electrode (TE) having a thickness of at least 90 nm. The TiN films are deposited at room temperature and annealed at 400 °C in an inert environment for at least 1 min in a rapid thermal annealing system. The room-temperature deposited TiN TE acts as a tensile stressor on the HZO film during the annealing process. The stress-inducing TiN TE is shown to inhibit the formation of the monoclinic phase during HZO crystallization, forming an orthorhombic phase that generates a large FE polarization, even at low process temperatures.

We report on the effect of the Hf0.5Zr0.5O2 (HZO) film thickness on the ferroelectric and dielectric properties using pulse write/read measurements. HZO films of thicknesses ranging from 5 to 20 nm were annealed at 400 °C for 1 min in a nitrogen ambient to be compatible with the back-end of the line thermal budget. As the HZO film thickness decreases, low-voltage operation (1.0 V or less) can be achieved without the dead layer effect, although switching polarization (Psw) tends to decrease due to the smaller grain size. Meanwhile, for 20-nm-thick HZO films prepared under the identical stress (similar TiN top electrode thickness and thermal budget), the Psw and dielectric constant are reduced because of additional monoclinic phase formation.

An important application of ferroelectric films is their incorporation into dynamic random-access memories (DRAMs) as the storage node capacitor dielectric. Dynamic random-access memories represent a large market that is experiencing strong growth, but they are particularly significant as the technology leader for semiconductor devices. As products move to higher and higher integration density, new developments are first introduced in DRAMs. The steady trend toward higher density has placed severe demands on the device designs, particularly with respect to “squeezing” the capacitor into the available space.

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