Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

Moïse, T. S.; Summerfelt, Scott R.; McAdams, H.; Aggarwal, S.; Udayakumar, K. R.; Celii, F. G.; Martin, J.S.; Xing, Guoqiang; Hall, L.; Taylor, Kelly; Hurd, Trace; Rodríguez, J. A.; Remack, K.; Khan, M.D.; Boku, K.; Stacey, Gemma; Yao, M.; Albrecht, M.; Zielinski, E. M.; Thakre, Mahesh; Kuchimanchi, S.; Thomas, Anthony; McKee, B.; Rickes, Jürgen T.; Wang, A.; Grace, James; Fong, J.; Lee, D.; Pietrzyk, Cezary; Lanham, Ralph; Gilbert, Stephen R.; Taylor, D. V.; Amano, Jun; Bailey, R.; Chu, Fan; Fox, Glen R.; Sun, Sheng; Davenport, Tom

doi:10.1109/iedm.2002.1175897

Cited by 32 publications

(11 citation statements)

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“…The PZT films studied in this paper were deposited by MOCVD on Ir bottom electrodes with Ir/Iroxide top electrodes. Additional fabrication and device details are described in [1].…”

Section: A Device Fabricationmentioning

confidence: 99%

“…A ferroelectric SPICE model is presented that can be used to accurately simulate hysteresis and switching polarization behavior. This model agrees with experimental data and can be used to simulate FRAM circuit behavior through "end of life".Embedded ferroelectric random access memory (FRAM) has become a viable non-volatile memory (NVM) for applications requiring low power consumption, fast write times, and high cycling endurance [1][2][3]. Over the past decade the technology has progressed to the point that high density ferroelectric memory is currently in production at the 130-nm node [4].…”

mentioning

confidence: 99%

“…Embedded ferroelectric random access memory (FRAM) has become a viable non-volatile memory (NVM) for applications requiring low power consumption, fast write times, and high cycling endurance [1][2][3]. Over the past decade the technology has progressed to the point that high density ferroelectric memory is currently in production at the 130-nm node [4].…”

mentioning

confidence: 99%

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Scaling reliability and modeling of ferroelectric capacitors

Acosta

Rodríguez

Obradovic

et al. 2010

2010 IEEE International Reliability Physics Symposium

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We report on reliability properties of MOCVD PZT ferroelectric capacitors as a function of film thickness. Data is presented for fatigue, thermal depolarization, and imprint. It is important to be able to model these parameters as they can significantly affect the switching polarization, which in turn affects the signal margin of an FRAM circuit. A ferroelectric SPICE model is presented that can be used to accurately simulate hysteresis and switching polarization behavior. This model agrees with experimental data and can be used to simulate FRAM circuit behavior through "end of life".Embedded ferroelectric random access memory (FRAM) has become a viable non-volatile memory (NVM) for applications requiring low power consumption, fast write times, and high cycling endurance [1][2][3]. Over the past decade the technology has progressed to the point that high density ferroelectric memory is currently in production at the 130-nm node [4]. Further scaling of the technology can enable an increase in storage capacity leading to new applications for FRAM [5]. However, there are several challenges that must first be overcome. The success of FRAM as a commercial non-volatile memory has been largely due to its integration into complementary metal-oxide-semiconductor (CMOS) technology. Therefore, FRAM must be able to scale along with CMOS technology if it is to continue as a practical NVM. One challenge is to maintain the reliability properties of the ferroelectric capacitor as the PZT thickness is scaled. These include the polarization loss due to read/write cycling, or fatigue, and data retention [6]. Data retention can be significantly affected by thermal depolarization (TD). This effect causes the polarization in a ferroelectric capacitor to decrease as the ambient temperature increases toward the Curie point [6].Also, as FRAM technology advances further, there is a need to design FRAM memory circuits that achieve the required performance and target reliability specifications. Thus, an additional challenge lies in the development of accurate models that can be used to simulate the hysteresis and switching properties of ferroelectric capacitors, including the effects of relaxation, imprint and thermal depolarization.In this work we report on FRAM capacitor reliability properties as a function of thickness scaling. Experimental data is presented which shows the effects of film thickness, fatigue, thermal depolarization, and imprint on ferroelectric capacitor behavior. These results indicate a need for an accurate model that can be used to simulate FRAM signal margin. A ferroelectric SPICE model based on a modified Preisach model (for hysteresis effect) is also presented, including a procedure for modeling the FRAM circuit reliability. Simulation results using our model closely resemble those obtained experimentally. I. EXPERIMENTAL DETAILS A. Device FabricationThe ferroelectric capacitors studied were processed with PZT thicknesses of 50-nm, 60-nm, 70-nm, and 90-nm. The 70-nm and 90-nm thick capacitors were fully integrated...

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“…The PZT films studied in this paper were deposited by MOCVD on Ir bottom electrodes with Ir/Iroxide top electrodes. Additional fabrication and device details are described in [1].…”

Section: A Device Fabricationmentioning

confidence: 99%

mentioning

confidence: 99%

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Scaling reliability and modeling of ferroelectric capacitors

Acosta

Rodríguez

Obradovic

et al. 2010

2010 IEEE International Reliability Physics Symposium

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“…For example, these ferroelectric oxide capacitor stacks have to be integrated with a conducting plug directly on top of the pass transis tor in the one-transistor-one-capacitor (1T-1C) cell of advanced ferroelectric memories. 40 Such a cell, which is currently being manufactured by Texas Instru ments, 40 is shown in the image in Figure 2. The ferroelectric capacitor stack must be deposited by a scalable process suited to manufacturing, such as chemical vapor deposition or sputtering.…”

Section: A Brief History Of Oxide Electronicsmentioning

confidence: 99%

Whither Oxide Electronics?

Ramesh¹,

Schlom²

2008

MRS Bull.

127

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In this issue we have endeavored to answer the question, "Whither oxide electronics?" This issue provides a framework and perspective on the progress in the field of oxide electronics over the past several decades, as well as the challenges and opportunities in the years to come. Building on the foundations laid by the pioneers in the materials community and spurred by the discovery of high-temperature superconductivity, there has been both tremendous progress in understanding the complex science of oxide electronic materials and the discovery of other fascinating new phenomena, including colossal magnetoresistance, multiferrocity, and twodimensional electron gases in correlated oxide systems. Thin-film heterostructures provide a pathway to create novel devices and combinations of physical phenomena. Indeed, the ability to synthesize and control oxide heterostructures using sophisticated deposition techniques has become a key enabler of the recent advances in this field. These oxides are beginning to enter mainstream products because of their higher performance, for example, ferroelectric memories and oxides with high dielectric constant for computers that run at higher speed and use less power.

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“…This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data. This chip's process technology features embedded ferroelectric capacitors that store data in a charge versus bias voltage hysteresis [3]. This hysteresis is shown in Fig.…”

mentioning

confidence: 99%

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

Qazi¹,

Amerasekera²,

Chandrakasan³

2013

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers

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TXNonvolatile processing-continuously operating a digital circuit and retaining state through frequent power interruptions-creates new applications for portable electronics operating from harvested energy [1] and high-performance systems managing power by operating "normally off" [2]. To enable these scenarios, energy processing must happen in parallel with information processing. This work makes the following contributions: 1) the design of a nonvolatile D flip-flop (NVDFF) with embedded ferroelectric capacitors (fecaps) that senses data robustly and avoids race conditions; 2) the integration of the NVDFF into the ASIC design flow with a power management unit (PMU) and a simple one-bit interface to brown-out detection circuitry; and 3) a characterization of the NVDFF statistical signal margin and the energy cost of retaining data. This chip's process technology features embedded ferroelectric capacitors that store data in a charge versus bias voltage hysteresis [3]. This hysteresis is shown in Fig. 1 along with the principle of self-timed sensing. Prior to sensing, the fecaps have been programmed to opposite data states, corresponding to opposite points on the zero bias voltage points of the hysteresis curve. Identical charging currents integrate the difference in remnant charge between the two fecaps onto nodes FET and FEC. The node to first cross the diode voltage drop plus a PMOS threshold will quickly pull the internal node of the sensing latch high. The ferroelectric capacitance is large compared to the internal node of the sensing latch, so a small voltage difference on the high capacitance nodes FET and FEC is converted to a large voltage difference on the latch nodes. In addition to being self-timed, this approach develops sufficient bias (1.1 V) before the fecaps are sensed. Fecap signal dynamics are exponentially sensitive to voltage bias [4], so it is important to avoid the performance penalty associated with sensing at low bias.The schematic of the nonvolatile latch in Fig. 2 shows the additional transistors for saving data, isolating fecaps during active operation, and protecting fecaps during power loss. This latch is combined as the slave stage with a clocked CMOS master latch to form the NVDFF in Fig. 3. The waveforms show how the ports PG, LD, EQ, and VDDNV need to be sequenced during power interruption. While active, PG=LD=0, and nodes FET and FEC act as a virtual supply for the slave latch. The save operation initiates when PG rises as CK is held low, cutting off VDDNV and enabling a weak pull-down path (M8-M10) to discharge one of the two fecaps (write "0") depending on the data state of the slave latch. The subsequent rise of LD preserves the data in the other fecap, which has already been written to a "1" during the previous restore operation. Prior to power loss, the EQ signal assertion clears floating voltages inside the slave latch, and then the VDDNV rail is discharged to prevent conducting paths to nodes FET/FEC. A complementary sequence is applied after VDD and VDDNV return high for ...

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Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

Cited by 32 publications

References 3 publications

Scaling reliability and modeling of ferroelectric capacitors

Scaling reliability and modeling of ferroelectric capacitors

Whither Oxide Electronics?

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems

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Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process

Cited by 32 publications

References 3 publications

Scaling reliability and modeling of ferroelectric capacitors

Scaling reliability and modeling of ferroelectric capacitors

Whither Oxide Electronics?

A 3.4pJ FeRAM-enabled D flip-flop in 0.13&#x00B5;m CMOS for nonvolatile processing in digital systems

Contact Info

Product

Resources

About

A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems