A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

Kushida, K.; Suzuki, Ai; Gou, Fujun; Kawasumi, A.; Hirabayashi, O.; Takeyama, Y.; Sasaki, Takahiro; Katayama, A.; Fujimura, Y.; Yabe, T.

doi:10.1109/jssc.2009.2014009

Cited by 43 publications

(12 citation statements)

References 9 publications

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“…This additional increase in the capacitance prevents faster bit-line discharge by an accessed SRAM cell and degrades the cell stability. This problem is remedied by isolating the accessed SRAM cell from the parasitic capacitance of the local assist circuitry as proposed by Kushida 2009 andSharma et al 2011.…”

Section: Stability Analysismentioning

confidence: 99%

“…The capacitance separator (isolates the parasitic capacitance) (Kushida 2009) immunizes the disturbing effect of parasitic capacitance in the accessed cell. In the beginning of a read cycle, the local bit-line swings rapidly because of the isolation of the local assist circuitry capacitance (approximately 30 %) compared to the scenario when there this no parasitic capacitance isolation.…”

Section: Stability Analysismentioning

confidence: 99%

“…The use of an additional global bit-line requires an extra metal resource which decreases the cell density. This problem is remedied by employing Cascaded BL architecture as proposed by Kushida et al 2009. With the capacitance separator (Cascaded BL) the effective bit-line capacitance for the accessed SRAM cell is reduced.…”

Section: Area Overheadmentioning

confidence: 99%

“…High bit density based hierarchy (Kushida et al 2009;Sharma et al 2012): alleviates the area overhead issue associated with the use of local assist circuit.…”

Section: Introductionmentioning

confidence: 99%

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Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

Sharma

Catthoor²,

Dehaene

2012

SRAM Design for Wireless Sensor Networks

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Section: Stability Analysismentioning

confidence: 99%

Section: Stability Analysismentioning

confidence: 99%

Section: Area Overheadmentioning

confidence: 99%

“…High bit density based hierarchy (Kushida et al 2009;Sharma et al 2012): alleviates the area overhead issue associated with the use of local assist circuit.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

Sharma

Catthoor²,

Dehaene

2012

SRAM Design for Wireless Sensor Networks

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“…Compared with super-threshold operation, in subthreshold region, alpha-particles or energetic cosmic rays can potentially induce soft errors more easily as is reduced, and Multiple Cell Upsets (MCU) may occur more frequently [37]. MCU can be reduced effectively by combining bit-interleaving architecture with Error Checking and Correction (ECC) technique [40]. The SRAM designs in [45], [46] use ECC technique to reduce soft errors and meet the required yield for low-voltage operation.…”

Section: Introductionmentioning

confidence: 99%

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Lin

Tsai

et al. 2012

IEEE J. Solid-State Circuits

153

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This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 µW power. Data is held down to 0.275 V with 2.29 µW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V. Index Terms-Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing.

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Energy Efficient Systems Using Resistive Memory Devices

Chang

Chiu

2013

Emerging Memory Technologies

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A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

Cited by 43 publications

References 9 publications

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Energy Efficient Systems Using Resistive Memory Devices

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