This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 µW power. Data is held down to 0.275 V with 2.29 µW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V. Index Terms-Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing.

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This paper provides a description of the hardware random number generator that is implemented on the IBM POWER7+i processor. We discuss the underlying mechanism using basic ring oscillator circuits implemented in standard digital logic circuits. The source of entropy is based on sampling phase jitter in the ring oscillators, and the rate of phase jitter accumulation is measured. We show that the design is simple and robust yet able to generate a high rate of random bits while using a minimum of logic area. The design is very resistant to physical manipulation, being able to produce solid entropy values under environmental conditions that exceed the requirements of the surrounding circuitry. With a design-specific mechanism to correct for ring oscillator sample bias, the output shows a very high rate of entropy, which is validated. IntroductionThis paper describes the design and implementation of the on-chip random number generator (RNG) on the IBM POWER7+ processor. The design was originally conceived for the purpose of client-server security where a random number is used when a secure communication channel is established in order to guard against replay attacks. In this context, it is important that the generated number is random in the sense that its value cannot be predicted, but because it is possible to guard against replay attacks by other means once the communication channel is established, the performance requirements of the RNG are modest. The objective of the RNG described in this paper was to ensure we could rely on RNG randomness from fundamental sources such as quantum thermal noise alone, rather than rely on sources of noise that can vary in practice, such as power supply noise. As described in the paper, the result is that when the RNG is used to generate a single random number upon initialization ( a Bnonce[), we have a high degree of confidence that this is indeed a true random number.Once implemented, the RNG was used for stochastic algorithms, such as Monte Carlo simulations. In this case, RNG performance is a key concern, as many different random numbers are often required in the course of a single calculation. Another important use is in computer security and cryptography. Many of the security algorithms require a very high level of entropy (randomness). In order to satisfy these types of uses, the RNGs were more extensively characterized to establish the tradeoff between the rate at which a single RNG was read out and the resulting randomness characteristics. As described in the paper, this design can produce in excess of 128 million random bits per second with a very high level of entropy. Motivation

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