A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Abstract

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Negative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 µW power. Data is held down to 0.275 V with 2.29 µW Standby power. The minimum energy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V. Index Terms-Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing.

Low-power half-select free single-ended 10 transistor SRAM cell

“…SBI9T and UDVS10T also employ the concept of decoupled read scheme, and so, RSNM for these circuits are comparable to that of the proposed DSPS10T. As mentioned in Tu et al (2012), an SRAM cell is considered to possess excellent read stability if its RSNM is about 25 % of V DD . The proposed design very nearly meets this criterion.…”

Leakage Analysis of a Low Power 10 Transistor SRAM Cell in 90 nm Technology

“…Several Read-decoupled and single ended SRAM cell architectures have been proposed in [12]- [15]. These architectures ensures low power operation, but failed to improve read and write delay considerably.…”

A design of low swing and multi threshold voltage based low power 12T SRAM cell

“…A single ended 9T SRAM cell [21] is shown in Fig. 1 The fully differential low power 10T SRAM [22] bit cell is shown in Fig.…”

“…The proposed SRAM cell has power delay products of 0.6371eÀ18 and 0.5721eÀ19 for write and read operations, respectively. The same table [14] 6.822 9.201 7T [15] 6.323 10.451 Sub threshold 7T [16] 10.033 14.611 8T [17] 11.432 15.402 Vertical stacked 8T [18] 10.663 15.011 9T [19] 12.644 16.633 9T in sub threshold region [20] 14.669 17.821 Single ended 9T [21] 11.421 13.442 Fully differential 10T [22] 9.754 12.877 PNP based differential 10T [23] 12.540 15.429 11T [24] 15 shows that even the access time of the proposed SRAM cell is high but the power delay product is lesser because of more reduction in total power dissipation as compared with the other existing SRAM cells. So from the above results it is evident that the 12T proposed SRAM cell can provide better power solution than the other existing SRAM cells for portable devices if area of the device is not of prime concern.…”

“…So from the above results it is evident that the 12T proposed SRAM cell can provide better power solution than the other existing SRAM cells for portable devices if area of the device is not of prime concern. [14] 6.294 9.257 7T [15] 7.197 10.013 Sub threshold 7T [16] 4.913 6.790 8T [17] 7.315 9.157 Vertical stacked 8T [18] 5.223 7.331 9T [19] 8.371 10.226 9T in sub threshold region [20] 4.280 7.016 Single ended 9T [21] 5.821 7.433 Fully differential 10T [22] 4.852 6.291 PNP based differential 10T [23] 4.374 6.195 11T [24] 3.893 5.033…”