True hardware random number generation implemented in the 32-nm SOI POWER7+ processor

Abstract

This paper provides a description of the hardware random number generator that is implemented on the IBM POWER7+i processor. We discuss the underlying mechanism using basic ring oscillator circuits implemented in standard digital logic circuits. The source of entropy is based on sampling phase jitter in the ring oscillators, and the rate of phase jitter accumulation is measured. We show that the design is simple and robust yet able to generate a high rate of random bits while using a minimum of logic area. The design is very resistant to physical manipulation, being able to produce solid entropy values under environmental conditions that exceed the requirements of the surrounding circuitry. With a design-specific mechanism to correct for ring oscillator sample bias, the output shows a very high rate of entropy, which is validated. IntroductionThis paper describes the design and implementation of the on-chip random number generator (RNG) on the IBM POWER7+ processor. The design was originally conceived for the purpose of client-server security where a random number is used when a secure communication channel is established in order to guard against replay attacks. In this context, it is important that the generated number is random in the sense that its value cannot be predicted, but because it is possible to guard against replay attacks by other means once the communication channel is established, the performance requirements of the RNG are modest. The objective of the RNG described in this paper was to ensure we could rely on RNG randomness from fundamental sources such as quantum thermal noise alone, rather than rely on sources of noise that can vary in practice, such as power supply noise. As described in the paper, the result is that when the RNG is used to generate a single random number upon initialization ( a Bnonce[), we have a high degree of confidence that this is indeed a true random number.Once implemented, the RNG was used for stochastic algorithms, such as Monte Carlo simulations. In this case, RNG performance is a key concern, as many different random numbers are often required in the course of a single calculation. Another important use is in computer security and cryptography. Many of the security algorithms require a very high level of entropy (randomness). In order to satisfy these types of uses, the RNGs were more extensively characterized to establish the tradeoff between the rate at which a single RNG was read out and the resulting randomness characteristics. As described in the paper, this design can produce in excess of 128 million random bits per second with a very high level of entropy. Motivation

Counterfeit Detection and Prevention in Additive Manufacturing Based on Unique Identification of Optical Fingerprints of Printed Structures

“…The raw amount of extracted bits from dataset-A, dataset-B, dataset-C, and dataset-D are 273000 (350x780), 217000 (350x620), 161000 (350x460), and 150500 (350x430) respectively. The entropy of the extracted bits can be increased using postprocessing methods while sacrificing the amount of bits [67], [68]. It should be noted that these lengths are achieved using only one printed transistor in the optical fingerprint while the existing printed electrical PUF provides 1-bit using 3 transistors and 2 resistors [19].…”

A Lightweight Isolation Mechanism for Secure Branch Predictors

“…Correspondingly, OS and hypervisor also have their own keys. Since there are many mature methods for hardware random generation [19,30], we assume these random numbers can be generated using a dedicated hardware mechanism.…”

Building a Modern TRNG

“…AMD [1], ARM [3], and IBM [27] are examples of ring oscillator TRNGs intended for high-security applications (see Section 5.1. )…”