A 64-channel ASIC for Time-of-Flight Positron Emission Tomography (TOF PET) imaging has been designed and simulated. The circuit is optimized for the readout of signals produced by the scintillation of a L(Y)SO crystal optically coupled to a silicon photomultiplier (SiPM). Developed in the framework of the EndoTOFPET-US collaboration [1], the ASIC is integrated in the external PET plate and performs timing, digitization and data transmission for 511 keV and lower-energy events due to Compton scattering.Multi-event buffering capability allows event rates up to 100 kHz per channel. The channel cell includes a low input impedance low-noise current conveyor and two trans-impedance amplifier branches separately optimized for energy and time resolution. Two voltage mode discriminators generate respectively a fast trigger for accurate timing and a signal for time-over-threshold calculation, used for charge measurement. The digitization of these signals is done by two low-power TDCs, providing coarse and fine time stamps that are saved into a local register and later managed by a global controller, which builds-up the 40-bit event data and runs the interface with the data acquisition back-end.Running at 160 MHz the chip yields a 50 ps time binning and dissipates 7 mW per channel (simulated for 40 kHz event rate p/channel) for high capacitance photodetectors (9 mm 2 active area Silicon Photomultiplier with 320 pF terminal capacitance). The minimum SNR of 23.5 dB expected with this capacitance should allow triggering on the first photoelectron to achieve the envisaged timing performance for a TOF-PET system.

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Summary The development of applications for high‐performance embedded systems is a long and error‐prone process because in addition to the required functionality, developers must consider various and often conflicting nonfunctional requirements such as performance and/or energy efficiency. The complexity of this process is further exacerbated by the multitude of target architectures and mapping tools. This article describes LARA, an aspect‐oriented programming language that allows programmers to convey domain‐specific knowledge and nonfunctional requirements to a toolchain composed of source‐to‐source transformers, compiler optimizers, and mapping/synthesis tools. LARA is sufficiently flexible to target different tools and host languages while also allowing the specification of compilation strategies to enable efficient generation of software code and hardware cores (using hardware description languages) for hybrid target architectures – a unique feature to the best of our knowledge not found in any other aspect‐oriented programming language. A key feature of LARA is its ability to deal with different models of join points, actions, and attributes. In this article, we describe the LARA approach and evaluate its impact on code instrumentation and analysis and on selecting critical code sections to be migrated to hardware accelerators for two embedded applications from industry. Copyright © 2014 John Wiley & Sons, Ltd.

This paper tests the assertion, popularized by Arida et al. (2005), that risks associated with the jurisdiction and currency inconvertibility are relevant determinants of the high level of short-term real interest rates in Brazil. The results are by and large unfavorable not only to their conjecture, but also to variants of their argument. The results further indicate that traditional monetary and fiscal factors are far more relevant to explain the level of short-term real interest rates than the binomial jurisdictional uncertainty/ currency inconvertibility is.
Esse paper testa a hipütese, popularizada por Arida et al. (2005), de que riscos associados à incerteza jurisdicional e incoversibilidade da moeda nacional são importantes determinantes dos altos níveis da taxa básica de juros no Brasil. Os resultados dos testes são bastante desfavoráveis não apenas a essa hipotese, mas também a variantes dela. Os resultados também indicam que fatores tradicionais fiscais e monetários são bem mais relevantes para explicar o nível da taxa básica de juros, em comparação ao par incerteza jurisdicional/incoversibilidade da moeda

Ahstract-A 64-channel ASIC for TOF PET imaging is pre sented. The circuit provides time and energy measurements of events produced by a SiPM coupled to a L(Y)SO fast scintillator.This ASIC is developed in the framework of the EndoTOFPET US collaboration as an option for the readout of external 200x200 mm plate detector, which consists of 3x3x15 mm crystals and 3x3 mm (active area) SiPMs. Using the chip with non-segmented and/or higher light yield crystals is possible. The same applies for photodetectors with different gain, polarity, or even higher dark count rate. The targeted 200 ps timing resolution for the system and the need for a low power consumption have driven the choice of a closed-loop amplifier input stage and a 50 ps time binning TDC based on analogue interpolation. A power consumption between 5 to 10 mW per channel is expected to guarantee a SNR of at least 20 dB for the single photon, using a SiPM with 320 pF terminal capacitance.

The Clear-PEM detector system is a compact positron emission mammography scanner with about 12000 channels aiming at high sensitivity and good spatial resolution. Front-end, Trigger, and Data Acquisition electronics are crucial components of this system. The on-detector front-end is implemented as a data-driven synchronous system that identifies and selects the analog signals whose energy is above a predefined threshold. The off-detector trigger logic uses digitized front-end data streams to compute pulse amplitudes and timing. Based on this information it generates a coincidence trigger signal that is used to initiate the conditioning and transfer of the relevant data to the data acquisition computer. To minimize dead-time, the data acquisition electronics makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system operates at 100-MHz clock frequency, and is capable of sustaining a data acquisition rate of 1 million events per second with an efficiency above 95%, at a total single photon background rate of 10 MHz. The basic component of the front-end system is a low-noise amplifier-multiplexer chip presently under development. The off-detector system is designed around a dual-bus crate backplane for fast intercommunication between the system boards. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates. Monte Carlo simulation results evaluating the trigger performance, as well as results of hardware simulations are presented, showing the correctness of the design and the implementation approach.

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