We present the experimental characterization of the TOFPET2, a readout and digitization ASIC for radiation detectors using Silicon Photomultipliers. The circuit is designed in CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in PET or other applications. The chip has quad-buffered TDCs and charge integration QDCs in each channel. The Coincidence Time Resolution (CTR) of 511 keV photon pairs from a 22Na point source measured with 2 × 2 × 3 mm3 LSO:Ce crystals co-doped with 0.2% Ca is 118 and 119 ps FWHM when using respectively the SiPMs NUVHD 40um from Fondazione Bruno Kessler (FBK) and the S14160-3050HS MPPC from Hamamatsu Photonics (HPK). The energy resolution obtained for the 511keV photopeak is 10.5 and 12% FWHM when using respectively the SiPMs PM3325-WB from KETEK and the QFBR-S4N44P164S from Broadcom Inc.
The Clear-PEM detector system is a compact positron emission mammography scanner with about 12000 channels aiming at high sensitivity and good spatial resolution. Front-end, Trigger, and Data Acquisition electronics are crucial components of this system. The on-detector front-end is implemented as a data-driven synchronous system that identifies and selects the analog signals whose energy is above a predefined threshold. The off-detector trigger logic uses digitized front-end data streams to compute pulse amplitudes and timing. Based on this information it generates a coincidence trigger signal that is used to initiate the conditioning and transfer of the relevant data to the data acquisition computer. To minimize dead-time, the data acquisition electronics makes extensive use of pipeline processing structures and derandomizer memories with multievent capacity. The system operates at 100-MHz clock frequency, and is capable of sustaining a data acquisition rate of 1 million events per second with an efficiency above 95%, at a total single photon background rate of 10 MHz. The basic component of the front-end system is a low-noise amplifier-multiplexer chip presently under development. The off-detector system is designed around a dual-bus crate backplane for fast intercommunication between the system boards. The trigger and data acquisition logic is implemented in large FPGAs with 4 million gates. Monte Carlo simulation results evaluating the trigger performance, as well as results of hardware simulations are presented, showing the correctness of the design and the implementation approach.
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