No abstract

No abstract

No abstract

The transition from a planar to a FinFET device structure has changed device doping requirements. The fin sidewall doping and activation, crystallinity control of the fin, junction profile and leakage control on the fin are new challenges. With continuous scaling of FinFET technology, the narrower fins become more prone to crystallinity damage by ion implant, and lead to increases in junction leakage and fin parasitic resistance. We have introduced hot implant as a superior doping technique to room-temperature implant for arsenic source drain extension (SDE) and halo implants on vertical narrow fins. We have demonstrated for the first time that hot SDE implant on 6nm CD vertical fins produced single crystalline fins and enabled 5x improvement in fin line resistance and more than 10x reduction in junction leakage compared with a room-temperature SDE implant.

In this paper, we first review the trends for advanced CMOS devices in terms of architectures and scalability. The paper highlights the key process challenges for planar MOSFET and FinFET device technologies. We emphasize the need for advanced implant solutions to enable device scaling and performance as well as variability improvement. Especially, we discuss the latest damage engineering solutions as well as materials modification techniques (e.g., contact and strain engineering) to reduce leakage, improve drive current and process margin with reduced variability. Finally, we briefly discuss the implications and new challenges coming from novel channel material devices (e.g., silicon-germanium, germanium, and III-V).