Advanced CMOS devices: Challenges and implant solutions

Abstract

In this paper, we first review the trends for advanced CMOS devices in terms of architectures and scalability. The paper highlights the key process challenges for planar MOSFET and FinFET device technologies. We emphasize the need for advanced implant solutions to enable device scaling and performance as well as variability improvement. Especially, we discuss the latest damage engineering solutions as well as materials modification techniques (e.g., contact and strain engineering) to reduce leakage, improve drive current and process margin with reduced variability. Finally, we briefly discuss the implications and new challenges coming from novel channel material devices (e.g., silicon-germanium, germanium, and III-V).

Wet chemical treatments of high purity Ge crystals for γ-ray detectors: Surface structure, passivation capabilities and air stability

“…For several years, this niche of application has been almost the only one where germanium was considered as leading material. Recently, the increasingly demanding miniaturization of electronic devices reached the intrinsic limit to the physical nature of silicon and a renewed interest in SiGe and Ge-based MOS-based devices can be perceived, as shown by literature appearing on this topic [1,2]. Ge displays higher mobility of carriers and lower bandgap than silicon, nevertheless has the remarkable disadvantage of a less efficient surface passivation.…”

The Challenges of Advanced CMOS Process from 2D to 3D

“…It was found that a narrow fin which is isolated from large crystal volume; surface proximity and the 3D structure make amorphous silicon recrystallization problematic. If the fin is completely amorphized, only a very small seed for recrystallization, which results in a defective growth, and it degrades the resistivity and drive current of the transistors [118,119]. Therefore, for 3D transistors, it is necessary to reduce the amorphization depth created by implantation as well as the annealing to minimize the fin damage.…”

Defect engineering for shallow n‐type junctions in germanium: Facts and fiction

“…Alternatively, one can consider the use of cold or cryogenic implantations , resulting in a more uniform damage profile and a thicker a‐Ge layer, with less point defects below the a/c interface in the end‐of‐range region. In the case of 10 keV As + implants at −50 °C this has led to the lowest sheet resistance after activation annealing at 600 °C, compared with RT or 400 °C implantations .…”