Cache memories embedded in most of complex processors significantly contribute to the global single event upset-induced error rate. Three different approaches allowing the study of this contribution by fault injection are investigated in this paper
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0018-9499International audienceAn approach to reproduce radiation ground testing results for the study of microprocessors vulnerability to single event upset (SEU) is described in this paper. Resulting cross-sections fit very well with measured ones
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