How to characterize the problem of SEU in processors &amp;amp; representative errors observed on flight

Velazco, Raoul; Ecoffet, R.; Faure, Fabien

doi:10.1109/iolts.2005.32

Cited by 16 publications

(5 citation statements)

References 6 publications

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“…According to statistics from National Aeronautics and Space Administration (NASA), particle radiation is the primary cause of anomalies in spacecraft operations [3]. The anti-SEU performance of SRAM in current research has been assessed mainly by the critical Linear Energy Transfer (LET) [4].…”

Section: Introductionmentioning

confidence: 99%

Research on heavy ion irradiation effects on SOI SRAM

Li,

Hao,

Zhao

et al. 2023

J. Inst.

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SRAM based on SOI devices has been widely used in aerospace storage devices due to its good electrical characteristics and radiation resistance. However, with the development of semiconductor technology, the feature size of devices continues to shrink, and the irradiation effects of high-energy ions have become increasingly serious. Single event effect has become the biggest threat to the failure of the spacecraft. A mixed-simulation method was used to research the heavy ion irradiation effects on SOI SRAM. SRAM consists of two coupled inverters. Firstly, the voltage changes of the inverter and SRAM output nodes under heavy ion irradiation were compared and analyzed, then the influence of the device itself and heavy ion parameters on the single particle flipping effect of the SRAM is investigated, and finally the necessary conditions for the flipping of the stored information in the SRAM are discussed and derived. The results show that heavy ion incidence does not permanently change the final state of the inverter; devices in the off state in the SRAM will undergo information flipping only when they are irradiated by heavy ions, and the threshold voltage of the N-type MOSFET is lower than that of the P-type MOSFET; an increase in the penetration depth will accelerate the flipping speed of the SRAM, but when the LET is high, the influence of the penetration depth on the flipping speed decreases; the change of the stored information in the SRAM is the result of the combined effect of pulse width and pulse height.

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Section: Introductionmentioning

confidence: 99%

Research on heavy ion irradiation effects on SOI SRAM

Li,

Hao,

Zhao

et al. 2023

J. Inst.

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“…SEUs are similar to SETs, but they affect the memory elements with bit-flips [2]. According to [4], SEUs have a very high occurrence probability and must be considered when designing embedded systems.…”

Section: Introductionmentioning

confidence: 99%

Characterization of a RISC-V System-on-Chip under Neutron Radiation

Santos

Luza

Kastriotou

et al. 2021

2021 16th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Systems for harsh environments often use embedded processors for tasks that require reliability. However, harsh environments cause faulty behavior in electronics, which eventually lead to system failure. Therefore, embedded processors must use techniques to improve their reliability. In this context, this work presents the implementation and characterization of a RISC-V-based system-on-chip. We characterized our implementation by carrying out test campaigns at the ChipIr irradiation facility. This facility provides a beamline for testing electronics against neutrons, mimicking atmospheric-like environments. With this first test campaign, we identified the most critical parts of our system-on-chip and essential tips to improve the test effectiveness. In the second test campaign, we used an improved version of the system setup with higher reliability error observability features. The version embedding all the hardening techniques could correct or mitigate 98.1 % of the detected upsets under irradiation.

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“…Nevertheless, space radiation environment poses a serious threat to electronic system. About 45% of the malfunctions in spacecraft were caused by space radiation environment, according to National Aeronautics and Space Administration (NASA) [1,2]. The irradiation resistance of SoC must be improved if we want to apply SoC to space electronic systems.…”

Section: Introductionmentioning

confidence: 99%

Primary Total Ionizing Dose Effect Studies on Xilinx SoC Irradiated with <sup>60</sup>Co γ Rays

Zhang

et al. 2014

AMM

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We designed radiation effect experimental system including current measurement section and functional test section for Xilinx Zynq-7010 System on chip (SoC) and performed the Total Ionizing Dose (TID) experiment irradiated by Co60 γ-source on the chip. At the dose rate of 0.04 Gy(Si)/s, the total dose of 1.69 kGy(Si), the current value in the experiment increased first and then decreased. The test board got functional interruption at the gamma dose of 1.69 kGy(Si). The function of the board normalized after room temperature annealing and 70°C high temperature annealing except that the current value decreased by 28% compared to the current before irradiation. The mechanisms for the first TID test results on Xilinx SoC were deduced and discussed.

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How to characterize the problem of SEU in processors & representative errors observed on flight

Cited by 16 publications

References 6 publications

Research on heavy ion irradiation effects on SOI SRAM

Research on heavy ion irradiation effects on SOI SRAM

Characterization of a RISC-V System-on-Chip under Neutron Radiation

Primary Total Ionizing Dose Effect Studies on Xilinx SoC Irradiated with <sup>60</sup>Co γ Rays

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