Single-event-upset-like fault injection: a comprehensive framework

Faure, Fabien; Velazco, Raoul; Peronnard, P.

doi:10.1109/tns.2005.860689

Cited by 19 publications

(4 citation statements)

References 12 publications

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“…A great deal of experiments have proved that such an estimation is very close to real measure as well as that the strategy can be successfully applied to advanced processors [63].…”

Section: Simulated Fault Injection Experimentsmentioning

confidence: 78%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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Abstract-New generation electronic devices have become more and more sensitive to the effects of the natural radiation coming from the surrounding environment. These radiation sources are cosmic rays and radioactive impurities, able to corrupt the content of memory cells or to induce transient pulses in combinational logic. The growing sensitivity seems to be related to two main factors: the lower and lower charge needed to define the logic levels in advanced devices and the increasing number of basic components inside the modern integrated circuits. In this paper, are described state-of-art techniques to mitigate these effects as well as typical tests to verify the radiation-tolerance of the devices and/or systems.

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“…A great deal of experiments have proved that such an estimation is very close to real measure as well as that the strategy can be successfully applied to advanced processors [63].…”

Section: Simulated Fault Injection Experimentsmentioning

confidence: 78%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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“…Such tests constitute a very popular technique to verify designs running in FPGAs. However, an actual environment should be emulated in such a way that bitflips must be injected in random cells following a temporal pattern compatible with a Poisson distribution with a specific mean time between failures (MTBF) [37]. Unfortunately, to the authors' knowledge, errors are typically just injected as SBUs since it is unusual to know the relation between logic and physical addresses to flip adjacent bits.…”

Section: B Applications On Seu Injection Testsmentioning

confidence: 99%

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

Fabero

Mecha

Franco

et al. 2020

IEEE Trans. Nucl. Sci.

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A sensitivity characterization of a Xilinx Artix-7 FPGA against 14.2 MeV neutrons is presented. The content of the internal SRAMs and flip-flops were downloaded in a PC and compared with a golden version of it. Flipped cells were identified and classified as cells of the configuration RAM, BRAM, or flip-flops. SBUs and MCUs with multiplicities ranging from 2 to 8 were identified using a statistical method. Possible shapes of multiple events are also investigated, showing a trend to follow wordlines. Finally, MUSCA SEP3 was used to make assesment for actual environments and an improvement of SEU injection test is proposed.

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“…An exponential distribution describes the time between events in a Poisson process, which occur continuously and independently at a constant average rate. This is very suitable for modeling fault injection times [7] as transient errors are infrequent and independent of earlier errors. During the simulation, the processor model iteratively injects transient faults based on the exponential distribution.…”

Section: Fault Injectionmentioning

confidence: 99%

A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs

Stralen

Pimentel

2012

Proceedings of the Eighth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

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With the reduction in feature size, transient errors start to play an important role in modern embedded systems. It is therefore important to make fault-tolerance a first-class citizen in embedded system design. Fault-tolerance patterns are techniques to make an application fault-tolerant. Not only do fault-tolerance patterns affect the quality of the embedded system (like performance, energy and cost), but there also are many ways of applying them. In this paper, we present the SAFE simulation framework that supports the early exploration of the different possibilities to apply faulttolerance patterns to MPSoC-based embedded multimedia systems. The SAFE model incorporates fault injection, detection and correction. As a result, a Pareto front can be obtained that not only shows the trade-off between metrics like performance, energy, cost, but also captures reliability metrics like frame drops due to soft errors and the number of unresolvable faults.

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Single-event-upset-like fault injection: a comprehensive framework

Cited by 19 publications

References 12 publications

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Single Event Upsets Under 14-MeV Neutrons in a 28-nm SRAM-Based FPGA in Static Mode

A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs

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