Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco, Raoul; Franco, Francisco J.

doi:10.1109/isie.2007.4375148

Cited by 15 publications

(14 citation statements)

References 59 publications

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“…The reason is their affordable cost and that many modern devices implement error detection and protection mechanisms, such as the well-known Error Correcting Codes (ECCs) [1], [2], which make them very reliable to the so-called Single Event Effects (SEEs) [3].…”

mentioning

confidence: 99%

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Clemente

Hubert

Franco

et al. 2017

IEEE Trans. Nucl. Sci.

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Abstract-This paper presents the characterization of the sensitivity to 14-MeV neutrons of a Commercial Off-The-Shelf (COTS) 90-nm Static Random Access Memories (SRAMs) manufactured by Cypress Semiconductor, when biased at ultra low voltage. Firstly, experiments exposing this memory at 14-MeV neutrons, when powering it up at bias voltages ranging from 0.5V to 3.3V, are presented and discussed. These results are in good concordance with theoretical predictions issued by the modeling tool MUSCA-SEP 3 (MUlti-SCAles Single Event Phenomena Predictive Platform). Then, this tool has been used to obtain Soft Error Rate (SER) predictions at different altitudes above the Earth's surface of this device vs. its bias voltage. Finally, the effect of contamination by α particles has also been estimated at said range of bias voltages.

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confidence: 99%

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Clemente

Hubert

Franco

et al. 2017

IEEE Trans. Nucl. Sci.

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“…Partially Run-time Reconfigurable (PRR) FPGAs suffer from reconfiguration delay and also susceptibility to the consequences of the Single Event Effects (SEEs) [4]. To alleviate the susceptibility to consequences of SEE, Fault Tolerance (FT) techniques are required to increase the reliability of a given design, but in most of the cases, they also come at the cost of degrading the system's performance.…”

Section: Introductionmentioning

confidence: 99%

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Ramezani

Sedaghat

Clemente

2017

IEEE Trans. VLSI Syst.

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Abstract-This study presents a technique to improve the reliability and the Mean Time to Failure (MTTF) of hardware task graphs running on reconfigurable computers. This technique, which has been named Task Early-fetch, can be applied to a sequence of one or several applications, represented as task graphs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous task graph, plus increasing the redundancy level of the early-fetched tasks. Experimental results on actual task graphs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant task graphs, and the improvement is more significant when applying to faulttolerant task graphs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at run-time and steers the execution of the running task graphs. It demonstrates that, with 0.03% consumption of FFs and LUTs and also 1.22% occupancy of BRAMs available on a Xilinx Virtex UltraScale XCVU095-2FFVA2104E FPGA, the required run-time computations can be carried out in negligible delays.

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“…Single Event Transients (SETs) are phenomena that occur in analog electronic devices after the pass of a flying charged particle [1]. The origin of this particle is usually associated with cosmic rays (E.g., military or aerospace applications), nuclear facilities, radioactive impurities (Thorium or uranium inside the silicon bulk), etc.…”

Section: Introductionmentioning

confidence: 99%

Load resistor as a worst-case parameter to investigate single-event transients in analog electronic devices

Lopez-Calle

Franco

Agapito

et al. 2011

Proceedings of the 8th Spanish Conference on Electron Devices, CDE'2011

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Abstract-One of the main phenomena that commit the reliability of analog electronic systems working in the outer space is the presence of energetic ions that produce spurious transients after crossing the device. These pulses are transmitted to the network loading the device and can eventually lead to dangerous situations as it has been observed in some spatial missions. This paper shows how the value of the resistor loading the device can affect the shape of the transients.

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Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Cited by 15 publications

References 59 publications

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Sensitivity Characterization of a COTS 90-nm SRAM at Ultra Low Bias Voltage

Reliability Improvement of Hardware Task Graphs via Configuration Early Fetch

Load resistor as a worst-case parameter to investigate single-event transients in analog electronic devices

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