Despite its long history, from Rent's rule [1] on, interconnect prediction is little used in industry.The most common implementation of interconnect prediction, the 'wireload model' used in synthesis, is almost universally scorned by the designers that use it. Even the canonical use of interconnect prediction, the decision of how many interconnect resources to put on a chip in the first place, is being replaced by experimentation over a set of existing designs. CAD companies are scrambling to replace any remaining interconnect prediction with estimates derived from global routing. Why is industry moving away from interconnect prediction?This paper examines some fundamental problems with interconnect estimation, and concludes that industrial practice will continue to rely on trial implementations rather than interconnect prediction.
The days when a router simply connected up the nets, obeying simple width and spacing rules, are long gone. While modern routers are still expected to connect things up correctly (albeit with a much more complex set of design rules), they are also expected to balance many more objectives. Even in a digital design, routers are now expected to preserve or enhance timing, get rid of crosstalk violations, even out metal density, insert redundant vias, minimize critical area, and generate 'litho friendly' geometry where possible, just to name a few additional tasks. Analog and mixed signal design adds many more, and more complex, constraints. Managing this large set of often conflicting objectives requires a router built for this express purpose. This talk will discuss Cadence's 'Space Based Router', a new router designed with DFM and DFY in mind.
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