Why interconnect prediction doesn't work

Scheffer, Lou; Nequist, Eric

doi:10.1145/333032.333044

Cited by 25 publications

(13 citation statements)

References 1 publication

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“…However, some popular algorithms such as min-cut placement and simulated annealing tend to produce very different placement solutions from run to run. Therefore information about timing-critical nets and nets that failed to route may be invalidated (similar reasons hamper interconnect prediction [19]). To facilitate incremental improvement of layout, we propose to stabilize placements from run to run.…”

Section: Introductionmentioning

confidence: 99%

On whitespace and stability in mixed-size placement and physical synthesis

Adya

Markov

Villarrubia

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool.In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade-off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis.In the context of earlier proposed techniques for mixed-size placement [2], we tune a state-of-the-art recursive bisection placer to better handle regular netlists that offer a convenient way to represent memories, datapaths and random-logic IP blocks. These modifications and better whitespace distribution improve results on recent mixed-size placement benchmarks.

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Section: Introductionmentioning

confidence: 99%

On whitespace and stability in mixed-size placement and physical synthesis

Adya

Markov

Villarrubia

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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“…WLMs are generally perceived to be inaccurate and to be inadequate for good optimization [7,8]. The traditional wisdom is that inaccuracy of WLMs will worsen as die sizes expand and feature sizes shrink, and wire loads become more dominant over pin loads (and less predictable).…”

Section: "Wlms Considered Harmful"mentioning

confidence: 99%

“…In the SLIP-2000 paper [8], Scheffer and Nequist make several compelling arguments as to why interconnect estimation (for which WLMs are just one exemplar) can never be successful. Order statistics arguments are used to justify the EDA industry shift to constructive (= global routing based) interconnect estimation: noisy estimators that are used to predict average-or sum-based metrics (e.g., total wire length) may be reasonably useful, but noisy estimators that are used to predict maximum-or minimum-based metrics (e.g., worst-case slack over all timing paths, or worst-case overcongestion over all global routing grids) will have large errors.…”

Section: Related Workmentioning

confidence: 99%

On the relevance of wire load models

Boese

Kahng

Mantik³

2001

Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction

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Wire load models (WLMs) are generally perceived to be inaccurate and inadequate for good optimization. The traditional wisdom is that accuracy of WLMs will worsen as die sizes expand and feature sizes shrink, and as wire loads become less predictable and more dominant over pin loads. In many industry white papers and academic works, the weaknesses of WLMs are used to motivate the unification of logic synthesis and physical layout into a single tool. We believe, however, that care must be taken in how we derive our motivations for new flows. In previous studies, evidence against WLMs was generally anecdotal or based on limited data (e.g., from a single design). Today, the maturation of Cadence Design Systems' PKS design tool affords us a unique opportunity to study WLMs in greater depth, and to quantify the timing improvements achieved by the unification of synthesis and layout. Using PKS, we have performed extensive experiments on fifteen real industry test cases. Our results confirm much of the conventional wisdom about WLMs, but also indicate that WLMs probably can still perform a useful function in the design flow.

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“…In [3] fast placement was used as an early timing feedback model for improved technology mapping. A possible reason for the poor exploration of our topic is [9]: this paper discourages interconnect prediction stating that the critical path is determined by the exceptional long wires, which are difficult to estimate. However, Monte Carlo simulations include these exceptions in a reasonably accurate way (see Section III).…”

Section: Introductionmentioning

confidence: 98%

Estimating circuit delays in FPGAs after technology mapping

Severens

Vansteenkiste

Heyse

et al. 2015

2015 25th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-An FPGA implementation requires a significant effort of the hardware designer, who optimizes FPGA designs by going through many time-consuming CAD flow iterations. These iterations provide two types of feedback: (1) the FPGA performance and (2) the identification of the parts having the highest impact on the FPGA performance. Both depend on the wirelength behavior. Studies have been dedicated to the estimation of local [5] and global [4] wirelengths, but to our knowledge both performance estimations and identification of the critical zone are not present in literature. Therefore this paper, firstly, presents a comparison of three performance estimation techniques: logic depth, Monte Carlo simulation and fast placement (ordered from low to high accuracy and runtime). Secondly, four methods identifying the critical zone are compared. Results show that Monte Carlo simulations provide a good identification of the parts having the highest impact on the performance. We conclude that Monte Carlo simulations provide useful feedback within a short runtime (about 30 times faster than placement), reducing the time-tomarket of FPGA implementations.

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Why interconnect prediction doesn't work

Cited by 25 publications

References 1 publication

On whitespace and stability in mixed-size placement and physical synthesis

On whitespace and stability in mixed-size placement and physical synthesis

On the relevance of wire load models

Estimating circuit delays in FPGAs after technology mapping

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