On whitespace and stability in mixed-size placement and physical synthesis

Abstract

In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible gate sizing, net buffering and detail placement require a certain amount of unused space in every region of the die. The need for "local" whitespace is further emphasized by temperature and power-density limits. Another requirement, the stability of placement results from run to run, is important to the convergence of physical synthesis loops. Indeed, logic resynthesis targetting local congestion in a given placement or particular critical paths may be irrelevant for another placement produced by the same or a different layout tool.In this work we offer solutions to the above problems. We show how to tie the results of a placer to a previously existing placement, and yet leave room for optimization. In our experiments this technique produces placements with similar congestion maps. We also show how to trade-off wirelength for routability by manipulating whitespace. Empirically, our techniques improve circuit delay of sparse layouts in conjunction with physical synthesis.In the context of earlier proposed techniques for mixed-size placement [2], we tune a state-of-the-art recursive bisection placer to better handle regular netlists that offer a convenient way to represent memories, datapaths and random-logic IP blocks. These modifications and better whitespace distribution improve results on recent mixed-size placement benchmarks.

Constructive benchmarking for placement

“…However, many designs today have surprisingly high amounts of whitespace, as illustrated and explained in [4,2]. In this new context, global positioning of cells is as important as their relative placement, and [4] proposes such techniques by means of analytical constraint generation (ACG) during top-down min-cut partitioning.…”

“…Moreover, it is unclear how to constructively improve the performance of a given placer on those benchmarks. In contrast, due to easy visual analysis of placer behavior on grids, such constructive improvements have been made in Capo [2]. We continue this work by giving a method to construct benchmarks amenable to such analysis.…”

“…Furthermore no clusters of logic exist in these benchmarks, and they are unaffected by global placement. Grid netlists [2] and the PEKO benchmarks are publicly available through the GSRC Bookshelf [9], and no existing placer comes close to optimal solutions on PEKO benchmarks. Moreover, it is unclear how to constructively improve the performance of a given placer on those benchmarks.…”

Fastplace 2.0: an efficient analytical placer for mixed-mode designs

“…Our algorithm was tested on the ISPD02 IBM-MS Mixedsize Placement Benchmarks [3][4][5]. These designs are relatively large and contain many macro blocks and standard cells.…”

Routability-driven placement and white space allocation

“…These placement tools include state-of-the-art academic tools Dragon 3.01 [22], CAPO 8.8 [6], Feng Shui 2.2 [2], and mPG 1.0 [11], a leading-edge industrial placement tools Cadence QPLACE (in SEULTRA 5.3). 1 All experiments are performed on the complete set of IBM-Dragon version 2 easy and hard benchmarks. These benchmarks were converted from ISPD98 [3] by mapping cells to commercial standard cell library by authors of Dragon [22] to evaluate routability of placements.…”