Wiring economy has successfully explained the individual placement of neurons in simple nervous systems like that of Caenorhabditis elegans [1-3] and the locations of coarser structures like cortical areas in complex vertebrate brains [4]. However, it remains unclear whether wiring economy can explain the placement of individual neurons in brains larger than that of C. elegans. Indeed, given the greater number of neuronal interconnections in larger brains, simply minimizing the length of connections results in unrealistic configurations, with multiple neurons occupying the same position in space. Avoiding such configurations, or volume exclusion, repels neurons from each other, thus counteracting wiring economy. Here we test whether wiring economy together with volume exclusion can explain the placement of neurons in a module of the Drosophila melanogaster brain known as lamina cartridge [5-13]. We used newly developed techniques for semiautomated reconstruction from serial electron microscopy (EM) [14] to obtain the shapes of neurons, the location of synapses, and the resultant synaptic connectivity. We show that wiring length minimization and volume exclusion together can explain the structure of the lamina microcircuit. Therefore, even in brains larger than that of C. elegans, at least for some circuits, optimization can play an important role in individual neuron placement.
Despite its long history, from Rent's rule [1] on, interconnect prediction is little used in industry.The most common implementation of interconnect prediction, the 'wireload model' used in synthesis, is almost universally scorned by the designers that use it. Even the canonical use of interconnect prediction, the decision of how many interconnect resources to put on a chip in the first place, is being replaced by experimentation over a set of existing designs. CAD companies are scrambling to replace any remaining interconnect prediction with estimates derived from global routing. Why is industry moving away from interconnect prediction?This paper examines some fundamental problems with interconnect estimation, and concludes that industrial practice will continue to rely on trial implementations rather than interconnect prediction.
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