Direct solution of performance constraints during placement

Chao, A.H.; Nequist, Eric; Vuong, Thi-Hong

doi:10.1109/cicc.1990.124811

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…6 The full timing graph [16] is 5 When recursive bisection is applied, careful choice of vertical versus horizontal cut direction is important, -one rule of thumb is to keep the aspect ratios of the blocks as close to a given constant (typically 1.0) as possible, for as long as possible. 6 Bidirectional pins can be captured using pairs of unidirectional pins and constrained timing graph traversals. built using the pins of the circuit as its vertices V = fv i g. Timing edges E = fe i j g that connect pins are constructed in two ways.…”

Section: Static Timing Analysismentioning

confidence: 99%

“…To first order, total (average) net length objectives correlate with congestion-and delay-related objectives (since wirelength creates capacitative load and RC delay). To bring the topology of timing constraints closer to placement, some works [17,6,14] minimize delays along explicitly enumerated paths, which becomes impractical when the number of signal paths undergoes combinatorial explosion in large circuits. 1 Combinatorial explosion is not a problem for static timing analysis methods [16,1] which can quickly determine whether delays along implicitly defined paths satisfy given timing constraints.…”

Section: Introductionmentioning

confidence: 99%

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Min-max placement for large-scale timing optimization

Kahng

Mantik

Markov

2002

Proceedings of the 2002 International Symposium on Physical Design

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At the 250nm technology node, interconnect delays account for over 40% of worst delays [12]. Transition to 130nm and below increases this figure, and hence the relative importance of timing-driven placement for VLSI. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timing-driven placement. Our placement algorithms have provable properties and are fast in practice. Empirical validation is based on extending a scalable min-cut placer with proven quality in wirelengthand congestion-driven placement [4]. The CPU overhead of the timingdriven capability is within 50%. We placed industrial circuits and evaluated the resulting layouts with a commercial static timing analyzer.

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Section: Static Timing Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Min-max placement for large-scale timing optimization

Kahng

Mantik

Markov

2002

Proceedings of the 2002 International Symposium on Physical Design

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“…3) Time Budgeting Among Blocks: One way of addressing timing closure of hierarchical block-based designs is to allocate timing budgets to all of the subsystem components, including the global interconnects [49], [50], [52], [55], [57], [62]. The obvious problem is that reasonable delay prediction for global interconnects is difficult, if not impossible, before the design is physically constructed.…”

Section: Timing Closurementioning

confidence: 99%

Limitations and challenges of computer-aided design technology for CMOS VLSI

et al. 2001

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As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semiautomated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density, performance, and power dissipation. One limitation is that the integrated circuit (IC) design process-like any other design process-involves practical tradeoffs among multiple objectives. For example, there is a need to design correct and testable chips in a very short time frame and for these chips to meet a competitive requirement. A second limitation is that the effectiveness of the design process is determined by its context-the design methodologies and flows we employ, and the designs that we essay-perhaps more than by its component tools and

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“…Our novel approach extends and improves upon Steiner heuristic called the single trunk Steiner tree (STST) [16], leveraging it for wiring and congestion estimation at the standard-cell level. Due to its linear computation time (as compared to O(nlogn) or more commonly O(n 2 ) for MST based approaches) the STST has been previously used for wirelength estimation [17][18][19], with [17] enhancing it to provide a O(nlogn) approximation, which is on average within 6% of the optimal. We show that our STST based approach allows for fast, yet accurate congestion/wiring estimation as well as prediction of the usage of specific layout shapes and patterns in standard cells.…”

Section: A Backgroundmentioning

confidence: 99%

A methodology for the early exploration of design rules for multiple-patterning technologies

Ghaida

Sahu

Kulkarni

et al. 2012

Proceedings of the International Conference on Computer-Aided Design

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Abstract-Double/Multiple-patterning (DP/MP) lithography in a multiple litho-etch steps process is a favorable solution for technology scaling to the 20nm node and below. Mask-assignment conflicts represent the biggest challenge for MP and limiting them through design rules is crucial for the adoption of MP technology. In this paper, we offer a methodology for the early evaluation and exploration of layout and MP rules intended for speeding up the rules-development cycle. Using a novel wiringestimation method, we create layout estimates with fine-grained congestion prediction. MP-conflicts are then predicted using a machine-learning approach. In this work, we demonstrate the use of the method for double-patterning lithography in litho-etchlitho-etch process; the methodology is more general, however, and can be applied for other multiple-patterning technologies including tripe/multiple-patterning with multiple litho-etch steps, selfaligned double patterning (SADP), and directed self-assembly. Results of testing the methodology on standard-cell layouts show an 81% accuracy in DP-conflicts prediction. The methodology was then used to explore DP and layout rules and investigate their effects on DP-compatibility and layout area. The methodology allows for rules optimization; for example, pushing the minimum tip-to-side same-color spacing rule value from 1.7× to 1.5× the minimum side-to-side spacing design rule (i.e., from 110nm down to 90nm) would more than double the number of DP-compatible cells in the library.

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Direct solution of performance constraints during placement

Cited by 6 publications

References 7 publications

Min-max placement for large-scale timing optimization

Min-max placement for large-scale timing optimization

Limitations and challenges of computer-aided design technology for CMOS VLSI

A methodology for the early exploration of design rules for multiple-patterning technologies

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