In this paper, a low-cost method to verify functional specifications of analog VLSI circuits is proposed. The method is based on the analysis of Lissajous signatures combined with regression techniques. In order to obtain Lissajous signatures, the observation space is partitioned into zones using hyperplanes, and a set of integer values used as the digital signature of the circuit is generated by Lissajous curve zone crossings. A predictor function obtained by nonlinear regression techniques predicts the functional specification parameters of the circuit under consideration. The viability of this methodology is analyzed and applied to verify the center frequency 0 of a bandpass biquad filter. Experimental measurements show an accurate prediction of the center frequency of the designed filter.
With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGAbased modulator.Index Terms-Field-programmable gate array (FPGA), multilevel active-clamped (MAC) converter, pulsewidth modulation (PWM).
This paper proposes a closed-loop control implementation fully-embedded into an FPGA for a permanent-magnet synchronous motor (PMSM) drive based on a four-level active-clamped converter. The proposed FPGA controller comprises a field-oriented control to drive the PMSM, a DC-link voltage balancing closed-loop control (VBC), and a virtual-vector-based modulator for a four-level active-clamped converter. The VBC and the modulator operate in consonance to preserve the DC-link capacitor voltages balanced. The FPGA design methodology is carefully described and the main aspects to achieve an optimal FPGA implementation using low resources are discussed. Experimental results under different operating conditions are presented to demonstrate the good performance and the feasibility of the proposed controller for motor-drive applications.
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