FPGA Implementation of a PWM for a Three-Phase DC–AC Multilevel Active-Clamped Converter

Abstract

With the aim to implement a suitable controller for a three-phase dc-ac multilevel active-clamped converter to enable its use in practice, and as a first step toward a full closed-loop converter control implementation into a single field-programmable gate array (FPGA) device, this paper presents the structure and features of an FPGA implementation of an appropriate pulsewidth modulation (PWM) strategy. The selected PWM strategy guarantees dc-link capacitor voltage balance in every switching cycle, and covers both the undermodulation and overmodulation regions. A flexible implementation is conceived, allowing the variation of important operating parameters, such as the modulation index and switching frequency, through a simple user interface. The key aspects to achieve an efficient and robust FPGA implementation are discussed. Experimental results in a four-level converter prototype controlled with an Altera Cyclone III device under different operating conditions match fairly well with the expected results obtained through simulation, thus verifying the accurate performance of the FPGAbased modulator.Index Terms-Field-programmable gate array (FPGA), multilevel active-clamped (MAC) converter, pulsewidth modulation (PWM).

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

“…Nowadays FPGAs are used in a wide range of applications. They were historically used for high-density and parallel computations as well as neural network accelerators [34], but also for power electronics applications [2]. Typically, FPGAs are designed with a hard-macro approach, repeating the optimized basic block so as to realize a huge-sized IP with enormous computational capability.…”

“…Initially, we carried out the measurements switching off all the peripherals and setting GPIOs in analog mode, then we activated only timer 3 (TIM3) and GPIO port B. The power consumption change is due to the peripheral used to implement the PWM controller and is scaled in BCD technology following equation (2). The resulting energies per task are: 16.69 pJ for eFPGA, 7576.8 pJ for PULPino, 0.267 pJ for ASIC and 3.185 pJ for STM32 as reported in Table IV.…”

“…Softwareprogrammable devices are probably the most commonly used digital controllers, thanks to their computation unit, useful configurable peripherals and relatively low cost. Since control application requirements have become more stringent from the viewpoint of processing time and the number of I/Os, many designers have opted for a combination of both softwareprogrammable and hardware-programmable devices [2]. In addition, software-programmable devices are not convenient to perform compute-intensive kernels due to their inherent sequential mode of operation, whereas hardware-programmable devices -thanks to their fixed parallel structure -enable one to improve the efficiency and timing performance -switching frequency - [3]- [5].…”

Designing and Testing Composite Energy Storage Systems for Regulating the Outputs of Linear Wave Energy Converters

“…Referring to Figure 10, each phase of the wave energy emulator consists of a DC supply, a low pass filter, a section of coils from a particular linear machine, an H-bridge inverter and related control circuitries. The H-bridge is controlled by signals produced from a field programmable gate array (FPGA) based controller with PWM methods [36][37][38]. The low pass filter is used to remove the high frequency PWM components from the output of the H-bridge.…”

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“…Many topologies have been introduced for multilevel inverters that utilized combination of active switches and multiple isolated or dependent DC sources to generate different voltage levels at the output [9][10][11][12][13][14][15][16][17].…”