On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Redox-based nanoionic resistive memory cells are one of the most promising emerging nanodevices for future information technology with applications for memory, logic and neuromorphic computing. Recently, the serendipitous discovery of the link between redox-based nanoionic-resistive memory cells and memristors and memristive devices has further intensified the research in this field. Here we show on both a theoretical and an experimental level that nanoionic-type memristive elements are inherently controlled by non-equilibrium states resulting in a nanobattery. As a result, the memristor theory must be extended to fit the observed non-zero-crossing I–V characteristics. The initial electromotive force of the nanobattery depends on the chemistry and the transport properties of the materials system but can also be introduced during redox-based nanoionic-resistive memory cell operations. The emf has a strong impact on the dynamic behaviour of nanoscale memories, and thus, its control is one of the key factors for future device development and accurate modelling.

The realization of logic operations within passive crossbar memory arrays is a promising approach to expand the fields of application of such architectures. Material implication was recently suggested as the basic function of memristive crossbar junctions, and single bipolar resistive switches (BRS) as well as complementary resistive switches (CRS) were shown to be capable of realizing this logical functionality. Based on a systematic analysis of the Boolean functions, we demonstrate here that 14 of 16 Boolean functions can be realized with a single BRS or CRS cell in at most three sequential cycles. Since the read-out step is independent of the logic operation steps, the result of the logic operation is directly stored to memory, making logic-in-memory applications feasible.

Emerging resistively switching devices are thought to enable ultradense passive nanocrossbar arrays for use as random access memories (ReRAM) by the end of the decade, both for embedded and mass storage applications. Moreover, ReRAMs offer inherent logic‐in‐memory (LIM) capabilities due to the nonvolatility of the devices and therefore great potential to reduce the communication between memory and calculation unit by alleviating the so‐called von Neumann bottleneck. A single bipolar resistive switching device is capable of performing 14 of 16 two input logic functions in the logic concept presented by Linn et al. (“CRS‐logic”). In this paper, five types of selectorless devices are considered to validate this CRS‐logic concept is experimentally by means of the IMP and AND logic operations. As reference device a TaO x ‐based ReRAM cell is considered, which is compared to three more advanced device configurations consisting either of a threshold supported resistive switch (TS‐ReRAM), a complementary switching device (CS), or a complementary resistive switch (CRS). It is shown that all of these devices offer the desired LIM behavior. Moreover, the feasibility of XOR and XNOR operations using a modified logic concept is applied for both CS and CRS devices and the pros and cons are discussed.

Abstract-Highly accurate and predictive models of resistive switching devices are needed to enable future memory and logic design. Widely used is the memristive modeling approach considering resistive switches as dynamical systems. Here we introduce three evaluation criteria for memristor models, checking for plausibility of the I-V characteristics, the presence of a sufficiently non-linearity of the switching kinetics, and the feasibility of predicting the behavior of two anti-serially connected devices correctly. We analyzed two classes of models: the first class comprises common linear memristor models and the second class widely used non-linear memristive models. The linear memristor models are based on Strukov's initial memristor model extended by different window functions, while the non-linear models include Pickett's physics-based memristor model and models derived thereof. This study reveals lacking predictivity of the first class of models, independent of the applied window function. Only the physics-based model is able to fulfill most of the basic evaluation criteria.

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Abstract-Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic 'sneak' currents are efficiently avoided. However, until now the CRS-based logic-inmemory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al. IndexTerms [7]. However, due to absence of a transistor as selector device, low resistive devices in the matrix cause parasitic currents, also called current sneak paths, which drastically limits the maximum array size [8]. Thus, either a bipolar rectifying selector device or a complementary resistive switch (CRS) [9] configuration is required to enable passive arrays. In terms of logic operations, there are three basic approaches based on ReRAM devices. The first one uses ReRAM devices as switchable interconnects. In the CMOL concept [10] for example, a sea of elementary CMOS cells, each consisting of two pass transistors and an inverter, is connected of discontinuous lines via ReRAM cells. A second approach uses crossbar arrays for look-up-tables (LUT) for field programmable gate arrays (FPGA) applying small crossbar arrays. For example in [11] such architecture was suggested to implement a resistive programmable logic array (PLA) logic block realizing a full adder. Moreover, in [12,13] a so-called memory-based computing approach using large crossbar arrays for multi-input-multi-output LUTs, which leads to reduced circuitry overhead, was suggested. A completely different approach was suggested by Borghetti et al. [14] using ReRAM cells as conditionally switchable sequential logic devices, allowing logic-in-memory operations directly. This concept was further developed and adopted for CRS cells to improve array compatibility [15]. However, up to now only basic logic functions such as IMP or NAND have been shown for this approach by means of memristive simulations [16]. On the o...

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