A Complementary Resistive Switch-Based Crossbar Array Adder

Abstract

Abstract-Redox-based resistive switching devices (ReRAM) are an emerging class of non-volatile storage elements suited for nanoscale memory applications. In terms of logic operations, ReRAM devices were suggested to be used as programmable interconnects, large-scale look-up tables or for sequential logic operations. However, without additional selector devices these approaches are not suited for use in large scale nanocrossbar memory arrays, which is the preferred architecture for ReRAM devices due to the minimum area consumption. To overcome this issue for the sequential logic approach, we recently introduced a novel concept, which is suited for passive crossbar arrays using complementary resistive switches (CRSs). CRS cells offer two high resistive storage states, and thus, parasitic 'sneak' currents are efficiently avoided. However, until now the CRS-based logic-inmemory approach was only shown to be able to perform basic Boolean logic operations using a single CRS cell. In this paper, we introduce two multi-bit adder schemes using the CRS-based logic-in-memory approach. We proof the concepts by means of SPICE simulations using a dynamical memristive device model of a ReRAM cell. Finally, we show the advantages of our novel adder concept in terms of step count and number of devices in comparison to a recently published adder approach, which applies the conventional ReRAM-based sequential logic concept introduced by Borghetti et al. IndexTerms [7]. However, due to absence of a transistor as selector device, low resistive devices in the matrix cause parasitic currents, also called current sneak paths, which drastically limits the maximum array size [8]. Thus, either a bipolar rectifying selector device or a complementary resistive switch (CRS) [9] configuration is required to enable passive arrays. In terms of logic operations, there are three basic approaches based on ReRAM devices. The first one uses ReRAM devices as switchable interconnects. In the CMOL concept [10] for example, a sea of elementary CMOS cells, each consisting of two pass transistors and an inverter, is connected of discontinuous lines via ReRAM cells. A second approach uses crossbar arrays for look-up-tables (LUT) for field programmable gate arrays (FPGA) applying small crossbar arrays. For example in [11] such architecture was suggested to implement a resistive programmable logic array (PLA) logic block realizing a full adder. Moreover, in [12,13] a so-called memory-based computing approach using large crossbar arrays for multi-input-multi-output LUTs, which leads to reduced circuitry overhead, was suggested. A completely different approach was suggested by Borghetti et al. [14] using ReRAM cells as conditionally switchable sequential logic devices, allowing logic-in-memory operations directly. This concept was further developed and adopted for CRS cells to improve array compatibility [15]. However, up to now only basic logic functions such as IMP or NAND have been shown for this approach by means of memristive simulations [16]. On the o...

A HfO2‐Based Complementary Switching Crossbar Adder

“…Thus, this approach is a logic-in-memory concept designed for CRS and CS arrays. Moreover, for this specifi c concept, two multibit crossbar adder concepts have been introduced by Siemon et al [ 28 ] In this paper, we demonstrate the CS operation in the Pt|HfO 2 |Hf|Pt stack with high endurance (10 9 cycles) and realize all CRS-logic functions during quasi-static and pulse characterization. Furthermore, the highly reliable Pt|HfO 2 |Hf|Pt CS devices are integrated into 1 × n passive crossbar arrays and two concepts for multi-bit adders are implemented experimentally under pulse conditions.…”

“…[ 28 ] The fi rst concept requires two arrays, one for auxiliary calculations and another for determining the intermediate and the fi nal sum. The PC Adder needs 2( N +1)+2 operation steps, where N is the bit length of the operands.…”

“…[ 28 ] To constitute negative numbers in the binary system, the complementary notation is used. One option is the one's complement.…”

In-memory adder functionality in 1S1R arrays

“…Later, we suggested a derived scheme which can be efficiently implemented using CRS devices [6,7]. The CRS logic approach enables realization of in-array additions using less devices and steps compared to the initial memristive approaches [8]. Here we show that the CRS adder concept can also be extended to 1S1R arrays, thus it is applicable for a wider range of memristive crossbar arrays.…”

Factored Forms for Memristive Material Implication Stateful Logic

“…where both and are given by (34). Notice that (34b) and (34c) are reduced to (23b) and (23c), respectively, when .…”