Complementary resistive switches for passive nanocrossbar memories

Abstract

On the road towards higher memory density and computer performance, a significant improvement in energy efficiency constitutes the dominant goal in future information technology. Passive crossbar arrays of memristive elements were suggested a decade ago as non-volatile random access memories (RAM) and can also be used for reconfigurable logic circuits. As such they represent an interesting alternative to the conventional von Neumann based computer chip architectures. Crossbar architectures hold the promise of a significant reduction in energy consumption because of their ultimate scaling potential and because they allow for a local fusion of logic and memory, thus avoiding energy consumption by data transfer on the chip. However, the expected paradigm change has not yet taken place because the general problem of selecting a designated cell within a passive crossbar array without interference from sneak-path currents through neighbouring cells has not yet been solved satisfactorily. Here we introduce a complementary resistive switch. It consists of two antiserial memristive elements and allows for the construction of large passive crossbar arrays by solving the sneak path problem in combination with a drastic reduction of the power consumption.

Unipolar resistive switching with forming-free and self-rectifying effects in Cu/HfO2/n-Si devices

“…[1][2][3][4] Unfortunately, sneak current issue, which refers to the undesired current through unselected cells and thus leads to misreading when reading the selected cell, is still a tough obstacle in real application of crossbar RRAMs. 1,5 This issue will be further exacerbate when the selected cell is in the high resistance state (HRS), whereas all unselected cells are in the low resistance state (LRS). In order to solve above issue, five methods have been proposed, including one transistor-one resistor structure (1T1R), 6,7 one diode-one resistor structure (1D1R), 8,9 one bidirectional selector-one resistor structure (1S1R), 10,11 complementary resistive switch (CRS), [12][13][14][15] and one resistor with self-rectifying effect.…”

Trilayer Tunnel Selectors for Memristor Memory Cells

“…For unipolar devices, the selector can be a diode, but for bipolar memristors, the selector needs to have a large and roughly symmetric i–v nonlinearity in order to block current flow in either direction at low voltage magnitudes while allowing a much larger (e.g., >100×) current at higher voltages. Therefore, two‐terminal selectors with a scalability comparable to that of memristors are essential to realize the large array sizes needed to be competitive with the bit densities of alternate NVM technologies 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13. Accordingly, a significant effort has recently introduced a variety of new selectors, including an Ovonic threshold switch,11, 14 a mixed ionic–electronic conductor,9 an insulator–metal‐transition5, 15, 16 selector, tunneling devices,12, 17, 18, 19, 20 and others 6, 13…”

Temperature induced complementary switching in titanium oxide resistive random access memory

“…Among the several emerging memory, resistive random access memory (RRAM) based on the resistive switching (RS) effect taking place in metal-insulator-metal (MIM) cells, has attracted renowned interests as a promising next generation nonvolatile memory owing to its simple constituents, high speed operation, nondestructive readout, low operation voltage, long retention time, and high scalability. [1][2][3][4][5][6][7] Binary transition metal oxides, such as SiO 2 , HfO 2 , TiO 2 , NiO, ZnO, Ta 2 O 5 , etc., [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] has been intensively investigated as an active layers in RRAM application, for their big advantage, like crystal structure and stoichiometry are more easily controlled than perovskite oxides that consist of more than three components. Two-terminal RRAM structure allow its integration in crossbar arrays, by accessing each memory cell through the selection of a word-line and a bit-line.…”