Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays

Rosezin, R.; Linn, Eike; Nielen, Lutz; Kügeler, C.; Bruchhaus, R.; Waser, Rainer

doi:10.1109/led.2010.2090127

Cited by 113 publications

(64 citation statements)

References 17 publications

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“…Reported switching times vary by orders of magnitude with values ranging from nanoseconds to milliseconds. [23][24][25][26][27][28][29] As seen in Fig. 6, once programmed into the on-state, even low voltages trigger switching in low current capacity filaments, but still show a delay before the maximum current is achieved.…”

Section: B Transient Response In the On-statementioning

confidence: 98%

The role of internal structure in the anomalous switching dynamics of metal-oxide/polymer resistive random access memories

Rocha

Leeuw

Meskers

et al. 2013

Journal of Applied Physics

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Articles you may be interested in Unipolar resistive switching in metal oxide/organic semiconductor non-volatile memories as a critical phenomenon J. Appl. Phys. 118, 205503 (2015); 10.1063/1.4936349Reproducible bipolar resistive switching in entire nitride AlN/n-GaN metal-insulator-semiconductor device and its mechanism Appl. Phys. Lett. 105, 193502 (2014) The dynamic response of a non-volatile, bistable resistive memory fabricated in the form of Al 2 O 3 /polymer diodes has been probed in both the off-and on-state using triangular and step voltage profiles. The results provide insight into the wide spread in switching times reported in the literature and explain an apparently anomalous behaviour of the on-state, namely the disappearance of the negative differential resistance region at high voltage scan rates which is commonly attributed to a "dead time" phenomenon. The off-state response follows closely the predictions based on a classical, two-layer capacitor description of the device. As voltage scan rates increase, the model predicts that the fraction of the applied voltage, V ox , appearing across the oxide decreases. Device responses to step voltages in both the off-and on-state show that switching events are characterized by a delay time. Coupling such delays to the lower values of V ox attained during fast scan rates, the anomalous observation in the on-state that, device currents decrease with increasing voltage scan rate, is readily explained. Assuming that a critical current is required to turn off a conducting channel in the oxide, a tentative model is suggested to explain the shift in the onset of negative differential resistance to lower voltages as the voltage scan rate increases. The findings also suggest that the fundamental limitations on the speed of operation of a bilayer resistive memory are the time-and voltage-dependences of the switch-on mechanism and not the switch-off process. V C 2013 American Institute of Physics. [http://dx

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Section: B Transient Response In the On-statementioning

confidence: 98%

The role of internal structure in the anomalous switching dynamics of metal-oxide/polymer resistive random access memories

Rocha

Leeuw

Meskers

et al. 2013

Journal of Applied Physics

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“…One thing we observed that, to measure the read current, it is depends on state of the device in memristor based array and as in CRS based array it is independent of content of the state. We compared the calculations obtained from paper [13]. We have obtained the perfect difference in comparison between memristor and CRS as demonstrated…”

Section: Sneak Path Current Analysismentioning

confidence: 87%

Nano crossbar array of Complementary Resistive Switches with nonlinear memristive characteristics

2014

IJAERD

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Abstract-Emerging solid state memory devices based on different materials and volatility has been widely acknowledged like NVRAMs (or Memristor).Evolution of new solid state ionic conductors and in particular (Memristor) brought impetus to the creation of new domain of larger storage capabilities for the future electronic systems. The achievements of these emerging technologies are kind of encouraging when compared with the existing memory types. Accordingly, a new memory architecture called Resistive Random Access Memory (ReRAM) memory faces challenges like sneak path current flowing through neighbouring cells which limits array size. To deal with such issue is to enforce a crossbar array using complementary resistive switch (CRS). CRS has recently been proclaimed as a great beneficiary to conventional charge based memories. But, the nanoscale advantage of these devices poses new challenges in designing such memories as well. In this paper, our purpose is to familiarize Memristor principle and a preliminary note on various understanding of Memristor is also described and a novel non-linear memristive based complementary resistive switch memory model for effective simulation and analysis. The CRS has two memristor connected in antiserially. Four different state of CRS which significantly reduces sneak path current as compared to memristor based architecture. Here, CRSs can be viewed as primary logic building block in array and two modes of resistance states of CRS stores the information. Thus, our aim is to elucidate as to how CRS is beneficial for reducing sneak path current.

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“…To solve the issue of sneak path currents (Section II-B), we propose a crossbar array architecture with two memristors in each cell with opposite polarities organized as complementary resistive switches, as also shown in [10], [11]. Moreover, to address the high write voltage problem (discussed in Section II-A), our CRS model uses the memristor model with voltage based state control (Section III-A).…”

Section: B Crs Modelmentioning

confidence: 99%

“…To measure these currents we apply read voltage for the selected row and measure the read current in the selected column, keeping other cells floating. Cadence Virtuoso is used to simulate the CRS model assuming a load resistance (R load ) of 100Ω, OFF resistance (R of f ) of 310kΩ and ON resistance (R on ) of 460Ω, as also used in [11]. The resulting currents are measured and compared using two different read currents: read currents when the cell is in OFF state (I read of f ) and ON state (I read on ).…”

Section: Sneak Path Analysismentioning

confidence: 99%

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

Yang

Mathew

Shafik

et al. 2014

IEEE Embedded Syst. Lett.

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Abstract-Resistive memory, also known as memristor, is recently emerging as a potential successor to traditional chargebased memories. However, the nanoscale features of these devices introduce challenges in modeling and simulation. In this paper, we propose a novel Verilog-A based complementary resistive switch memory model for effective simulation and analysis. Our proposed model captures desired non-linear characteristics using voltage based state control as opposed to recently proposed current based state control. We demonstrate that such state control has advantages for our proposed CRS model based crossbar arrays in terms of symmetric ON/OFF voltages and significantly reduced sneak path currents with high noise margin compared to traditional memristor based architectures. Moreover, to validate the effectiveness of our Verilog-A based model we carry out extensive simulations and analyses for different crossbar array architectures using traditional EDA tools.

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Integrated Complementary Resistive Switches for Passive High-Density Nanocrossbar Arrays

Cited by 113 publications

References 17 publications

The role of internal structure in the anomalous switching dynamics of metal-oxide/polymer resistive random access memories

The role of internal structure in the anomalous switching dynamics of metal-oxide/polymer resistive random access memories

Nano crossbar array of Complementary Resistive Switches with nonlinear memristive characteristics

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis

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