Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An altemate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.
MechanicaI reliability is widely recognized as the primary obstacle to productization of porous low-k materials. The combination of weak bulk and interfacial properties with increasingly complex geometries poses a considerable challenge at the 65-nm node. The final solution must be sufficiently robust so as to ensure compatibility with multiple substrate types, interconnect configurations and packages. In this work, material engineering, modeling, design rule tailoring, and assembly optimization are employed to achieve required assembly reliability for both wirebond and flip-chip packages, for both bulk and SO1 substrates.
This paper compares three different schemes to pattern dual damascene (DD) structures. The Self Aligned (SA), Via First (VF), and Trench First (TF) architectures are compared in terms of complexity, process latitude, and sensitivity to lithography misalignment using 0.18-pm copper/oxide two metal level structures. The integration of thick metal lines is also discussed, for the upper levels of interconnects. This study shows that the VF architecture has the best via chain yield, regardless of the test configuration, and allows to pattern thick metal DD structures with high yield. The VF technique was used to manufacture a six copper level device, with functional yield similar to that obtained with an AICu/HSQ Back End Of Line (BEOL).
ExperimentalThe present work was performed in a 200-mm copper dedicated line. Minimum feature sizes used for this study are 0.32 pm for both the vias and the metal lines, with a minimum space of 0.32 pm. Metal line thickness is 0.5 pm for lower levels, and 0.8 pm for upper levels. The effect of line/via misalignment was studied on specific test structures described in [6]. This work only deals with the top misalignment, between a via and the upper metal level, which was seen to be most influent on via resistance and via chain yield.
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