Demonstration of an extendable and industrial 300mm BEOL integration for the 65-mn technology node

Abstract

Given the much discussed challenges of interconnect scaling at the 65-nm node, the choice of process architecture is a key determinant of performance and extendibility. An altemate trench-first with hardmask integration is described in this work, including subsequent benefits. BEOL design rules are detailed for the 65-nm architecture, supporting both "low-k and "ultra-low-k" backends, satisfying RC scaling requirements. Electrical parametric performance and yield are presented for a fully-integrated 300mm backend utilizing 65-nm design rules demonstrating the viability of this architecture for the 65-nm node and beyond.

Alignment robustness for 90 nm and 65 nm node through copper alignment mark integration optimization

“…The metal hard mask is etched after trench photolithography. After planarization by an organic BARC, the via layer is patterned on the shallow hard mask topography [8]. It should be noted here that in previous work the stacked SPM marks performance improvement was demonstrated in a copper BEOL integration without a hardmask.…”

Low‐kMaterials: Recent Advances

“…Although strip (resist removal) damage can be minimized with the use of hardmasks (the lithographic pattern is first transferred to the hardmask, which allows a PR strip without exposing the ILD) [29,30,[102][103][104][105], plasma damage arising from the actual ILD etch cannot be neglected. This damage manifests itself in the form of oxidative degradation of the ILD and as a result produces silica-based oxides and hydroxides at the exposed surfaces.…”

New etch challenges for the 65-nm technology node Low-k integration using An enhanced Trench First Hard Mask architecture

“…The most commonly published integration scheme is dual-inlaid "Via First Trench Last" (VFTL), which however suffers from resist poisoning and numerous processing challenges [2]. An enabling "Trench First with Hard Mask" (TFHM) approach has been presented as an alternative in providing greater compatibility with low-k materials for the 65nm technology node and beyond [2]. Based on this last integration scheme, an enhanced TFHM integration architecture has recently been proposed [3].…”

“…Various methods have been proposed (either the trench or the via can be etched first) for integrating the many steps involved in patterning low-k dielectric preserving its properties and avoiding or reducing copper interconnect contamination [1]. The most commonly published integration scheme is dual-inlaid "Via First Trench Last" (VFTL), which however suffers from resist poisoning and numerous processing challenges [2]. An enabling "Trench First with Hard Mask" (TFHM) approach has been presented as an alternative in providing greater compatibility with low-k materials for the 65nm technology node and beyond [2].…”