Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types

Goldberg, C.; Downey, S.; Fiori, Vincent; Fox, Robert; Hess, Kai‐Uwe; Hinsinger, O.; Humbert, A.; Jacquemin, J.P.; Lee, S.; Lhuillier, Jérémy; Orain, S.; Pozder, Scott; Proenca, L.; Quercia, Fabien; Sabouret, E.; Tran, Tu Anh; Uehling, Trent

doi:10.1109/iitc.2005.1499902

Cited by 18 publications

(7 citation statements)

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“…Packaging processes such as dicing, wirebonding, and flip-chip die attach can damage the low-k dielectrics due to mechanical stress [186][187][188][189][190][191][192][193][194]. Standard tests for assessing the reliability of packaged parts include high-temperature storage, temperature-humidity-bias, high-temperature operating life (HTOL), and thermal cycle (Table 8.3).…”

Section: Package Reliabilitymentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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Section: Package Reliabilitymentioning

confidence: 99%

Process Technology for Copper Interconnects

Gambino

2012

Handbook of Thin Film Deposition

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“…13. [2] The largest CTE mismatch interface can be found in two areas, which are (a) the interface between LM-2 ILD (one first layer using SiO 2 ILD material) and LM-3 ILD layers (the last layer using low-k ILD material), and (b) the interface between M1 ILD (the first layer using low-k ILD material) and Contact ILD layer which uses doped SiO 2 as ILD material. The stress applied at the interface between LM-2 and LM-3 is not as large as compared to that between M1 and contact ILD layer because the thickness of LM-3 ILD layer is greater than that of Metal1 ILD layer.…”

Section: Mechanical Stress Analysis For Actual Delaminated Interfacementioning

confidence: 99%

“…The two major weakness of the low-k material, which are the inherently weaker bulk mechanical and fracture-strength properties, and lower interfacial adhesion strength in the silicon stack-up, pose significant challenges to downstream wafer testing and packaging process and material selection. [1,2,3,4 and 5] 1 illustrates the cross-section of cavity-down Tape Ball Grid Array package (TBGA) that uses polyimide tape based substrate. TBGA substrate is based on a one-metal layer or multiple-metal layers laminated on a polyimide tape which is attached to an internal heat spreader.…”

Section: Introductionmentioning

confidence: 99%

Challenges in cavity-down thermally enhanced packages containing low-k die

Lee¹,

Tran²,

Yuan³

et al. 2010

2010 12th Electronics Packaging Technology Conference

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The cavity-down thermally enhanced package such as Tape Ball Grid Array (TBGA) has the best thermal performance among the high pin count wire bonded package types because the silicon is attached directly onto a thick internal heat spreader. The TBGA package with low-k/Cu wafers has however challenged the assembly industry in passing package qualification requirement especially temperature cycling requirement. Low-k interlayer dielectric (ILD) material usually has the dielectric constant k of less than 3. The inherently weak adhesion in the low-k interconnect stack-up makes the silicon more susceptible to a failure mode called ILD crack or delamination that causes electrical failure during temperature related excursion such as temperature cycling test and board-level mounting. ILD delamination failure was reported not only at the die corner with highest stress concentration, but also on the die side away from the corner. Optical inspection of dicing quality at failing areas showed similar level of back-end-of-line (BEOL) peeling through scribe test structures that would have passed reliability testing when assembling in a conventional plastic ball grid array (PBGA). Mechanical analyses were performed to identify the specific failing interface within the stack of the back-end-of-line (BEOL) in the low-k die. 3D finite element model simulations were performed to analyze the stress distribution in the low-k die area. Structural parameters of the cavity-down TBGA package were modulated. The simulation analysis indicated that TBGA package applies a tensile stress on the top portion of the die edge region where the inter-layer dielectric (ILD) stacks are located when the package is subjected to temperature cycling tests. The tensile stress on the top portion of the die can be reduced by varying specific structural parameters of the TBGA package. A series of experiments was designed and conducted to validate the prediction of the mechanical simulation model. The simulation analysis supported by empirical data explained as to why the TBGA package is more susceptible to ILD delamination failures in temperature excursion condition in the presence of or lack of dicing defects. A special low stress glob top material was formulated and demonstrated a good production capability and package level reliability. The knowledge of the stress distribution in the TBGA system enabled the development of low stress glob top encapsulant that demonstrated a good production capability and package level reliability.

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“…The reduction in metal pitch, however, degrades the interconnect RC delay, which tends to curtail the benefits of interconnect scaling. The semiconductor industry is now focusing its efforts on implementing ultra low K (ULK) porous dielectric materials (k < 2.5) into Cu interconnects to reduce the interconnect capacitance and cross-talk noise and enhance circuit performance [2]. However, the introduction of these fragile ULK materials coupled with the legal requirement to remove lead containing materials from the chip and package present significant challenges to product reliability due to the weak mechanical properties of ULK materials interacting with rigid lead free bumps.…”

Section: Introductionmentioning

confidence: 99%

Chip package interaction (CPI) reliability of low-k/ULK interconnect with lead free technology

Anand

et al. 2010

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC)

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The introduction of low-k/ultra-low-k (ULK) dielectric materials to accommodate the continuous scaling-down of the feature sizes of IC chips to improve the device density and performance of the ultra-large scale integrated (ULSI) circuits represents great silicon and packaging integration challenges due to the weak mechanical properties of interlayer dielectric material (ILD). Implementation of crackstop and improve low-k/ULK mechanical properties are very effective to protect ILD crack propagation and delamination. Finite element analysis (FEA) simulation and Shadow Moire measurements showed higher die stress with lead free bumps.Reflow simulated Shadow Moire measurements show a large warpage change from 150C to 25C, good control of the ramp rate is needed. Die warpage releases 50% after 30 days.

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Integration of a mechanically reliable 65-nm node technology for low-k and ULK interconnects with various substrate and package types

Cited by 18 publications

References 1 publication

Process Technology for Copper Interconnects

Process Technology for Copper Interconnects

Challenges in cavity-down thermally enhanced packages containing low-k die

Chip package interaction (CPI) reliability of low-k/ULK interconnect with lead free technology

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