This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators.
This paper presents an architecture wherein multiple delta-sigma modulators are combined so that neither time oversampling nor time interleaving are necessary. For a system containing M Pthorder delta-sigma modulators, approximately P bits of accuracy are gained for every doubling of M . Thus, the resolution gained by combining M delta-sigma modulators is approximately the same as that with the same modulator with an oversampling rate of M. Measured results from a 16-channel parallel delta-sigma A/D converter composed of second-order delta-sigma modulators verify the theory and demonstrate that this architecture retains much of the robustness of the individual delta-sigma modulators to non-ideal circuit behavior. I. The Parallel AX A/D Converter ArchitectureThe parallel delta-sigma (IIAE) A/D converter architecture is shown in Fig. 1 [1 ,2]. The analog input z(n) is simultaneously applied to M modulators each followed by a conventional delta-sigma modulator. The AC modulator outputs are then filtered, demodulated and summed together to produce a single digital output sequence. In the c,onventional AC A/D converter both the signal and quantization noise pass through the same filter and therefore, both are filtered by the lowpass decimation filter, Fig. 2(a). In contrast, the IIAX A/D converter filters out much of the quantization error contributed by the AX modulators without filtering the input signal and without oversampling, Fig. 2(b). I e o ( n J I Hadamard sequence is referred to as Hadamard modulation. The Hadamard modulation is especially well suited for implementation since it consists solely of plus and minus ones. Thus depending on the value of the Hadamard sequence, the analog input signal and the digital output sequence are either passed or inverted.Figure 2: The signal and quantization signal paths for (a) the conventional delta-sigma modulator and (b) the parallel delta-sigma modulator.For a given number of channels (M), filter length and A E modulator, the power 'of the overall quantization error component can be determined using Fig. 3. For example, for a thiry-two channel II A E A/D converter with third-order AX modulators, and filters of length-190 or greater, Fig. 3 indicates that P, is 81 dR below A2 where A is the quantizer step size and P, is the. power in the quantization. To calculate the minimum number of bits, R, that a iiniform quantizer A/D converter would require to achieve the same mean squared A/D conversion error as the IIAE A/D converter, we use the approximate formula [5] Figure 1 : The parallel delta-sigma architecture.where 7 is the maximum absolute value of the IIAC modiilator input sequence. For A = 1 and 7 = 0.3, the converThe sequences u,(n), 0 5 T 5 M -1, are referred to sion accuracy of the IIAE A/D converter for the example as Hadamard sequences and the process of multiplying by a above corresponds to about 11 bits. 23.3.1 503 IEEE 1994 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-1886-2/94 $3.00 0 1994 IEEE
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